SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#CPU_SCS_CPU_SCS_MAP1_TABLE_1 lists the memory-mapped registers for the CPU_SCS registers. All register offset addresses not listed in #CPU_SCS_CPU_SCS_MAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Complex bit access types are encoded to fit into small table cells. #CPU_SCS_CPU_SCS_MAP1_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
ICTR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICTR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICTR_TABLE.
Return to the Summary Table.
Interrupt Control Type
Read this register to see the number of interrupt lines that the NVIC supports.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INTLINESNUM | ||||||
| R-0h | R-1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2-0 | INTLINESNUM | R | 1h | Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2: 65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256 |
ACTLR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ACTLR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ACTLR_TABLE.
Return to the Summary Table.
Auxiliary Control
This register is used to disable certain aspects of functionality within the processor
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DISOOFP | DISFPCA | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DISFOLD | DISDEFWBUF | DISMCYCINT | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 9 | DISOOFP | R/W | 0h | Disables floating point instructions completing out of order with respect to integer instructions. |
| 8 | DISFPCA | R/W | 0h | Disable automatic update of CONTROL.FPCA |
| 7-3 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | DISFOLD | R/W | 0h | Disables folding of IT instruction. |
| 1 | DISDEFWBUF | R/W | 0h | Disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed. |
| 0 | DISMCYCINT | R/W | 0h | Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs. |
STCSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCSR_TABLE.
Return to the Summary Table.
SysTick Control and Status
This register enables the SysTick features and returns status flags related to SysTick.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | COUNTFLAG | ||||||
| R-0h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLKSOURCE | TICKINT | ENABLE | ||||
| R-0h | R-1h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 16 | COUNTFLAG | R | 0h | Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the **AHB-AP** Control Register is set to 0. Otherwise, COUNTFLAG is not changed by the debugger read. |
| 15-3 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | CLKSOURCE | R | 1h | Clock source: 0: External reference clock. 1: Core clock External clock is not available in this device. Writes to this field will be ignored. |
| 1 | TICKINT | R/W | 0h | 0: Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero. 1: Counting down to zero pends the SysTick handler. |
| 0 | ENABLE | R/W | 0h | Enable SysTick counter 0: Counter disabled 1: Counter operates in a multi-shot way. That is, counter loads with the Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads STRVR.RELOAD again, and begins counting. |
STRVR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STRVR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STRVR_TABLE.
Return to the Summary Table.
SysTick Reload Value
This register is used to specify the start value to load into the current value register STCVR.CURRENT when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and STCSR.COUNTFLAG are activated when counting from 1 to 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RELOAD | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23-0 | RELOAD | R/W | X | Value to load into the SysTick Current Value Register STCVR.CURRENT when the counter reaches 0. |
STCVR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCVR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCVR_TABLE.
Return to the Summary Table.
SysTick Current Value
Read from this register returns the current value of SysTick counter. Writing to this register resets the SysTick counter (as well as STCSR.COUNTFLAG).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CURRENT | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23-0 | CURRENT | R/W | X | Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears STCSR.COUNTFLAG. |
STCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STCR_TABLE.
Return to the Summary Table.
SysTick Calibration Value
Used to enable software to scale to any required speed using divide and multiply.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NOREF | SKEW | RESERVED | |||||
| R-1h | R-1h | R-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TENMS | |||||||
| R-00075300h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TENMS | |||||||
| R-00075300h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TENMS | |||||||
| R-00075300h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | NOREF | R | 1h | Reads as one. Indicates that no separate reference clock is provided. |
| 30 | SKEW | R | 1h | Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. |
| 29-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23-0 | TENMS | R | 00075300h | An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. The value read is valid only when core clock is at 48MHz. |
NVIC_ISER0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER0_TABLE.
Return to the Summary Table.
Irq 0 to 31 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SETENA31 | SETENA30 | SETENA29 | SETENA28 | SETENA27 | SETENA26 | SETENA25 | SETENA24 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SETENA23 | SETENA22 | SETENA21 | SETENA20 | SETENA19 | SETENA18 | SETENA17 | SETENA16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SETENA15 | SETENA14 | SETENA13 | SETENA12 | SETENA11 | SETENA10 | SETENA9 | SETENA8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SETENA7 | SETENA6 | SETENA5 | SETENA4 | SETENA3 | SETENA2 | SETENA1 | SETENA0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | SETENA31 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. |
| 30 | SETENA30 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. |
| 29 | SETENA29 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. |
| 28 | SETENA28 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. |
| 27 | SETENA27 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. |
| 26 | SETENA26 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. |
| 25 | SETENA25 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. |
| 24 | SETENA24 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. |
| 23 | SETENA23 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. |
| 22 | SETENA22 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. |
| 21 | SETENA21 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. |
| 20 | SETENA20 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. |
| 19 | SETENA19 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. |
| 18 | SETENA18 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. |
| 17 | SETENA17 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. |
| 16 | SETENA16 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. |
| 15 | SETENA15 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. |
| 14 | SETENA14 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. |
| 13 | SETENA13 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. |
| 12 | SETENA12 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. |
| 11 | SETENA11 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. |
| 10 | SETENA10 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. |
| 9 | SETENA9 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. |
| 8 | SETENA8 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. |
| 7 | SETENA7 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. |
| 6 | SETENA6 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. |
| 5 | SETENA5 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. |
| 4 | SETENA4 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. |
| 3 | SETENA3 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. |
| 2 | SETENA2 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. |
| 1 | SETENA1 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. |
| 0 | SETENA0 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. |
NVIC_ISER1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISER1_TABLE.
Return to the Summary Table.
Irq 32 to 63 Set Enable
This register is used to enable interrupts and determine which interrupts are currently enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SETENA37 | SETENA36 | SETENA35 | SETENA34 | SETENA33 | SETENA32 | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | SETENA37 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state. |
| 4 | SETENA36 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state. |
| 3 | SETENA35 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state. |
| 2 | SETENA34 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state. |
| 1 | SETENA33 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. |
| 0 | SETENA32 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit enables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. |
NVIC_ICER0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER0_TABLE.
Return to the Summary Table.
Irq 0 to 31 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLRENA31 | CLRENA30 | CLRENA29 | CLRENA28 | CLRENA27 | CLRENA26 | CLRENA25 | CLRENA24 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLRENA23 | CLRENA22 | CLRENA21 | CLRENA20 | CLRENA19 | CLRENA18 | CLRENA17 | CLRENA16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLRENA15 | CLRENA14 | CLRENA13 | CLRENA12 | CLRENA11 | CLRENA10 | CLRENA9 | CLRENA8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLRENA7 | CLRENA6 | CLRENA5 | CLRENA4 | CLRENA3 | CLRENA2 | CLRENA1 | CLRENA0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLRENA31 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current enable state. |
| 30 | CLRENA30 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current enable state. |
| 29 | CLRENA29 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current enable state. |
| 28 | CLRENA28 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current enable state. |
| 27 | CLRENA27 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current enable state. |
| 26 | CLRENA26 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current enable state. |
| 25 | CLRENA25 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current enable state. |
| 24 | CLRENA24 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current enable state. |
| 23 | CLRENA23 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current enable state. |
| 22 | CLRENA22 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current enable state. |
| 21 | CLRENA21 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current enable state. |
| 20 | CLRENA20 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current enable state. |
| 19 | CLRENA19 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current enable state. |
| 18 | CLRENA18 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current enable state. |
| 17 | CLRENA17 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current enable state. |
| 16 | CLRENA16 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current enable state. |
| 15 | CLRENA15 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current enable state. |
| 14 | CLRENA14 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current enable state. |
| 13 | CLRENA13 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current enable state. |
| 12 | CLRENA12 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current enable state. |
| 11 | CLRENA11 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current enable state. |
| 10 | CLRENA10 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current enable state. |
| 9 | CLRENA9 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current enable state. |
| 8 | CLRENA8 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current enable state. |
| 7 | CLRENA7 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current enable state. |
| 6 | CLRENA6 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current enable state. |
| 5 | CLRENA5 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current enable state. |
| 4 | CLRENA4 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current enable state. |
| 3 | CLRENA3 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current enable state. |
| 2 | CLRENA2 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current enable state. |
| 1 | CLRENA1 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current enable state. |
| 0 | CLRENA0 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current enable state. |
NVIC_ICER1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICER1_TABLE.
Return to the Summary Table.
Irq 32 to 63 Clear Enable
This register is used to disable interrupts and determine which interrupts are currently enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLRENA37 | CLRENA36 | CLRENA35 | CLRENA34 | CLRENA33 | CLRENA32 | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | CLRENA37 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current enable state. |
| 4 | CLRENA36 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current enable state. |
| 3 | CLRENA35 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current enable state. |
| 2 | CLRENA34 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current enable state. |
| 1 | CLRENA33 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current enable state. |
| 0 | CLRENA32 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit disables the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current enable state. |
NVIC_ISPR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR0_TABLE.
Return to the Summary Table.
Irq 0 to 31 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently pending.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| SETPEND31 | SETPEND30 | SETPEND29 | SETPEND28 | SETPEND27 | SETPEND26 | SETPEND25 | SETPEND24 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SETPEND23 | SETPEND22 | SETPEND21 | SETPEND20 | SETPEND19 | SETPEND18 | SETPEND17 | SETPEND16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SETPEND15 | SETPEND14 | SETPEND13 | SETPEND12 | SETPEND11 | SETPEND10 | SETPEND9 | SETPEND8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SETPEND7 | SETPEND6 | SETPEND5 | SETPEND4 | SETPEND3 | SETPEND2 | SETPEND1 | SETPEND0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | SETPEND31 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. |
| 30 | SETPEND30 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. |
| 29 | SETPEND29 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. |
| 28 | SETPEND28 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. |
| 27 | SETPEND27 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. |
| 26 | SETPEND26 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. |
| 25 | SETPEND25 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. |
| 24 | SETPEND24 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. |
| 23 | SETPEND23 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. |
| 22 | SETPEND22 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. |
| 21 | SETPEND21 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. |
| 20 | SETPEND20 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. |
| 19 | SETPEND19 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. |
| 18 | SETPEND18 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. |
| 17 | SETPEND17 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. |
| 16 | SETPEND16 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. |
| 15 | SETPEND15 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. |
| 14 | SETPEND14 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. |
| 13 | SETPEND13 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. |
| 12 | SETPEND12 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. |
| 11 | SETPEND11 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. |
| 10 | SETPEND10 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. |
| 9 | SETPEND9 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. |
| 8 | SETPEND8 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. |
| 7 | SETPEND7 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. |
| 6 | SETPEND6 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. |
| 5 | SETPEND5 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. |
| 4 | SETPEND4 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. |
| 3 | SETPEND3 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. |
| 2 | SETPEND2 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. |
| 1 | SETPEND1 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. |
| 0 | SETPEND0 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. |
NVIC_ISPR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ISPR1_TABLE.
Return to the Summary Table.
Irq 32 to 63 Set Pending
This register is used to force interrupts into the pending state and determine which interrupts are currently pending.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SETPEND37 | SETPEND36 | SETPEND35 | SETPEND34 | SETPEND33 | SETPEND32 | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | SETPEND37 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state. |
| 4 | SETPEND36 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state. |
| 3 | SETPEND35 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state. |
| 2 | SETPEND34 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state. |
| 1 | SETPEND33 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. |
| 0 | SETPEND32 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit pends the interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. |
NVIC_ICPR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR0_TABLE.
Return to the Summary Table.
Irq 0 to 31 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLRPEND31 | CLRPEND30 | CLRPEND29 | CLRPEND28 | CLRPEND27 | CLRPEND26 | CLRPEND25 | CLRPEND24 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLRPEND23 | CLRPEND22 | CLRPEND21 | CLRPEND20 | CLRPEND19 | CLRPEND18 | CLRPEND17 | CLRPEND16 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLRPEND15 | CLRPEND14 | CLRPEND13 | CLRPEND12 | CLRPEND11 | CLRPEND10 | CLRPEND9 | CLRPEND8 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLRPEND7 | CLRPEND6 | CLRPEND5 | CLRPEND4 | CLRPEND3 | CLRPEND2 | CLRPEND1 | CLRPEND0 |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLRPEND31 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit returns its current state. |
| 30 | CLRPEND30 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit returns its current state. |
| 29 | CLRPEND29 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit returns its current state. |
| 28 | CLRPEND28 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit returns its current state. |
| 27 | CLRPEND27 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit returns its current state. |
| 26 | CLRPEND26 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit returns its current state. |
| 25 | CLRPEND25 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit returns its current state. |
| 24 | CLRPEND24 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit returns its current state. |
| 23 | CLRPEND23 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit returns its current state. |
| 22 | CLRPEND22 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit returns its current state. |
| 21 | CLRPEND21 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit returns its current state. |
| 20 | CLRPEND20 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit returns its current state. |
| 19 | CLRPEND19 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit returns its current state. |
| 18 | CLRPEND18 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit returns its current state. |
| 17 | CLRPEND17 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit returns its current state. |
| 16 | CLRPEND16 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit returns its current state. |
| 15 | CLRPEND15 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit returns its current state. |
| 14 | CLRPEND14 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit returns its current state. |
| 13 | CLRPEND13 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit returns its current state. |
| 12 | CLRPEND12 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit returns its current state. |
| 11 | CLRPEND11 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit returns its current state. |
| 10 | CLRPEND10 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit returns its current state. |
| 9 | CLRPEND9 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit returns its current state. |
| 8 | CLRPEND8 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit returns its current state. |
| 7 | CLRPEND7 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit returns its current state. |
| 6 | CLRPEND6 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit returns its current state. |
| 5 | CLRPEND5 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit returns its current state. |
| 4 | CLRPEND4 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit returns its current state. |
| 3 | CLRPEND3 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit returns its current state. |
| 2 | CLRPEND2 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit returns its current state. |
| 1 | CLRPEND1 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit returns its current state. |
| 0 | CLRPEND0 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit returns its current state. |
NVIC_ICPR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_ICPR1_TABLE.
Return to the Summary Table.
Irq 32 to 63 Clear Pending
This register is used to clear pending interrupts and determine which interrupts are currently pending.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CLRPEND37 | CLRPEND36 | CLRPEND35 | CLRPEND34 | CLRPEND33 | CLRPEND32 | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | CLRPEND37 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit returns its current state. |
| 4 | CLRPEND36 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit returns its current state. |
| 3 | CLRPEND35 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit returns its current state. |
| 2 | CLRPEND34 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit returns its current state. |
| 1 | CLRPEND33 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit returns its current state. |
| 0 | CLRPEND32 | R/W | 0h | Writing 0 to this bit has no effect, writing 1 to this bit clears the corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit returns its current state. |
NVIC_IABR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR0_TABLE.
Return to the Summary Table.
Irq 0 to 31 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ACTIVE31 | ACTIVE30 | ACTIVE29 | ACTIVE28 | ACTIVE27 | ACTIVE26 | ACTIVE25 | ACTIVE24 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ACTIVE23 | ACTIVE22 | ACTIVE21 | ACTIVE20 | ACTIVE19 | ACTIVE18 | ACTIVE17 | ACTIVE16 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ACTIVE15 | ACTIVE14 | ACTIVE13 | ACTIVE12 | ACTIVE11 | ACTIVE10 | ACTIVE9 | ACTIVE8 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ACTIVE7 | ACTIVE6 | ACTIVE5 | ACTIVE4 | ACTIVE3 | ACTIVE2 | ACTIVE1 | ACTIVE0 |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | ACTIVE31 | R | 0h | Reading 0 from this bit implies that interrupt line 31 is not active. Reading 1 from this bit implies that the interrupt line 31 is active (See EVENT:CPUIRQSEL31.EV for details). |
| 30 | ACTIVE30 | R | 0h | Reading 0 from this bit implies that interrupt line 30 is not active. Reading 1 from this bit implies that the interrupt line 30 is active (See EVENT:CPUIRQSEL30.EV for details). |
| 29 | ACTIVE29 | R | 0h | Reading 0 from this bit implies that interrupt line 29 is not active. Reading 1 from this bit implies that the interrupt line 29 is active (See EVENT:CPUIRQSEL29.EV for details). |
| 28 | ACTIVE28 | R | 0h | Reading 0 from this bit implies that interrupt line 28 is not active. Reading 1 from this bit implies that the interrupt line 28 is active (See EVENT:CPUIRQSEL28.EV for details). |
| 27 | ACTIVE27 | R | 0h | Reading 0 from this bit implies that interrupt line 27 is not active. Reading 1 from this bit implies that the interrupt line 27 is active (See EVENT:CPUIRQSEL27.EV for details). |
| 26 | ACTIVE26 | R | 0h | Reading 0 from this bit implies that interrupt line 26 is not active. Reading 1 from this bit implies that the interrupt line 26 is active (See EVENT:CPUIRQSEL26.EV for details). |
| 25 | ACTIVE25 | R | 0h | Reading 0 from this bit implies that interrupt line 25 is not active. Reading 1 from this bit implies that the interrupt line 25 is active (See EVENT:CPUIRQSEL25.EV for details). |
| 24 | ACTIVE24 | R | 0h | Reading 0 from this bit implies that interrupt line 24 is not active. Reading 1 from this bit implies that the interrupt line 24 is active (See EVENT:CPUIRQSEL24.EV for details). |
| 23 | ACTIVE23 | R | 0h | Reading 0 from this bit implies that interrupt line 23 is not active. Reading 1 from this bit implies that the interrupt line 23 is active (See EVENT:CPUIRQSEL23.EV for details). |
| 22 | ACTIVE22 | R | 0h | Reading 0 from this bit implies that interrupt line 22 is not active. Reading 1 from this bit implies that the interrupt line 22 is active (See EVENT:CPUIRQSEL22.EV for details). |
| 21 | ACTIVE21 | R | 0h | Reading 0 from this bit implies that interrupt line 21 is not active. Reading 1 from this bit implies that the interrupt line 21 is active (See EVENT:CPUIRQSEL21.EV for details). |
| 20 | ACTIVE20 | R | 0h | Reading 0 from this bit implies that interrupt line 20 is not active. Reading 1 from this bit implies that the interrupt line 20 is active (See EVENT:CPUIRQSEL20.EV for details). |
| 19 | ACTIVE19 | R | 0h | Reading 0 from this bit implies that interrupt line 19 is not active. Reading 1 from this bit implies that the interrupt line 19 is active (See EVENT:CPUIRQSEL19.EV for details). |
| 18 | ACTIVE18 | R | 0h | Reading 0 from this bit implies that interrupt line 18 is not active. Reading 1 from this bit implies that the interrupt line 18 is active (See EVENT:CPUIRQSEL18.EV for details). |
| 17 | ACTIVE17 | R | 0h | Reading 0 from this bit implies that interrupt line 17 is not active. Reading 1 from this bit implies that the interrupt line 17 is active (See EVENT:CPUIRQSEL17.EV for details). |
| 16 | ACTIVE16 | R | 0h | Reading 0 from this bit implies that interrupt line 16 is not active. Reading 1 from this bit implies that the interrupt line 16 is active (See EVENT:CPUIRQSEL16.EV for details). |
| 15 | ACTIVE15 | R | 0h | Reading 0 from this bit implies that interrupt line 15 is not active. Reading 1 from this bit implies that the interrupt line 15 is active (See EVENT:CPUIRQSEL15.EV for details). |
| 14 | ACTIVE14 | R | 0h | Reading 0 from this bit implies that interrupt line 14 is not active. Reading 1 from this bit implies that the interrupt line 14 is active (See EVENT:CPUIRQSEL14.EV for details). |
| 13 | ACTIVE13 | R | 0h | Reading 0 from this bit implies that interrupt line 13 is not active. Reading 1 from this bit implies that the interrupt line 13 is active (See EVENT:CPUIRQSEL13.EV for details). |
| 12 | ACTIVE12 | R | 0h | Reading 0 from this bit implies that interrupt line 12 is not active. Reading 1 from this bit implies that the interrupt line 12 is active (See EVENT:CPUIRQSEL12.EV for details). |
| 11 | ACTIVE11 | R | 0h | Reading 0 from this bit implies that interrupt line 11 is not active. Reading 1 from this bit implies that the interrupt line 11 is active (See EVENT:CPUIRQSEL11.EV for details). |
| 10 | ACTIVE10 | R | 0h | Reading 0 from this bit implies that interrupt line 10 is not active. Reading 1 from this bit implies that the interrupt line 10 is active (See EVENT:CPUIRQSEL10.EV for details). |
| 9 | ACTIVE9 | R | 0h | Reading 0 from this bit implies that interrupt line 9 is not active. Reading 1 from this bit implies that the interrupt line 9 is active (See EVENT:CPUIRQSEL9.EV for details). |
| 8 | ACTIVE8 | R | 0h | Reading 0 from this bit implies that interrupt line 8 is not active. Reading 1 from this bit implies that the interrupt line 8 is active (See EVENT:CPUIRQSEL8.EV for details). |
| 7 | ACTIVE7 | R | 0h | Reading 0 from this bit implies that interrupt line 7 is not active. Reading 1 from this bit implies that the interrupt line 7 is active (See EVENT:CPUIRQSEL7.EV for details). |
| 6 | ACTIVE6 | R | 0h | Reading 0 from this bit implies that interrupt line 6 is not active. Reading 1 from this bit implies that the interrupt line 6 is active (See EVENT:CPUIRQSEL6.EV for details). |
| 5 | ACTIVE5 | R | 0h | Reading 0 from this bit implies that interrupt line 5 is not active. Reading 1 from this bit implies that the interrupt line 5 is active (See EVENT:CPUIRQSEL5.EV for details). |
| 4 | ACTIVE4 | R | 0h | Reading 0 from this bit implies that interrupt line 4 is not active. Reading 1 from this bit implies that the interrupt line 4 is active (See EVENT:CPUIRQSEL4.EV for details). |
| 3 | ACTIVE3 | R | 0h | Reading 0 from this bit implies that interrupt line 3 is not active. Reading 1 from this bit implies that the interrupt line 3 is active (See EVENT:CPUIRQSEL3.EV for details). |
| 2 | ACTIVE2 | R | 0h | Reading 0 from this bit implies that interrupt line 2 is not active. Reading 1 from this bit implies that the interrupt line 2 is active (See EVENT:CPUIRQSEL2.EV for details). |
| 1 | ACTIVE1 | R | 0h | Reading 0 from this bit implies that interrupt line 1 is not active. Reading 1 from this bit implies that the interrupt line 1 is active (See EVENT:CPUIRQSEL1.EV for details). |
| 0 | ACTIVE0 | R | 0h | Reading 0 from this bit implies that interrupt line 0 is not active. Reading 1 from this bit implies that the interrupt line 0 is active (See EVENT:CPUIRQSEL0.EV for details). |
NVIC_IABR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IABR1_TABLE.
Return to the Summary Table.
Irq 32 to 63 Active Bit
This register is used to determine which interrupts are active. Each flag in the register corresponds to one interrupt.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ACTIVE37 | ACTIVE36 | ACTIVE35 | ACTIVE34 | ACTIVE33 | ACTIVE32 | |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | ACTIVE37 | R | 0h | Reading 0 from this bit implies that interrupt line 37 is not active. Reading 1 from this bit implies that the interrupt line 37 is active (See EVENT:CPUIRQSEL37.EV for details). |
| 4 | ACTIVE36 | R | 0h | Reading 0 from this bit implies that interrupt line 36 is not active. Reading 1 from this bit implies that the interrupt line 36 is active (See EVENT:CPUIRQSEL36.EV for details). |
| 3 | ACTIVE35 | R | 0h | Reading 0 from this bit implies that interrupt line 35 is not active. Reading 1 from this bit implies that the interrupt line 35 is active (See EVENT:CPUIRQSEL35.EV for details). |
| 2 | ACTIVE34 | R | 0h | Reading 0 from this bit implies that interrupt line 34 is not active. Reading 1 from this bit implies that the interrupt line 34 is active (See EVENT:CPUIRQSEL34.EV for details). |
| 1 | ACTIVE33 | R | 0h | Reading 0 from this bit implies that interrupt line 33 is not active. Reading 1 from this bit implies that the interrupt line 33 is active (See EVENT:CPUIRQSEL33.EV for details). |
| 0 | ACTIVE32 | R | 0h | Reading 0 from this bit implies that interrupt line 32 is not active. Reading 1 from this bit implies that the interrupt line 32 is active (See EVENT:CPUIRQSEL32.EV for details). |
NVIC_IPR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR0_TABLE.
Return to the Summary Table.
Irq 0 to 3 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_3 | PRI_2 | PRI_1 | PRI_0 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_3 | R/W | 0h | Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). |
| 23-16 | PRI_2 | R/W | 0h | Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). |
| 15-8 | PRI_1 | R/W | 0h | Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). |
| 7-0 | PRI_0 | R/W | 0h | Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). |
NVIC_IPR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR1_TABLE.
Return to the Summary Table.
Irq 4 to 7 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_7 | PRI_6 | PRI_5 | PRI_4 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_7 | R/W | 0h | Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). |
| 23-16 | PRI_6 | R/W | 0h | Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). |
| 15-8 | PRI_5 | R/W | 0h | Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). |
| 7-0 | PRI_4 | R/W | 0h | Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). |
NVIC_IPR2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR2_TABLE.
Return to the Summary Table.
Irq 8 to 11 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_11 | PRI_10 | PRI_9 | PRI_8 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_11 | R/W | 0h | Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). |
| 23-16 | PRI_10 | R/W | 0h | Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). |
| 15-8 | PRI_9 | R/W | 0h | Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). |
| 7-0 | PRI_8 | R/W | 0h | Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). |
NVIC_IPR3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR3_TABLE.
Return to the Summary Table.
Irq 12 to 15 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_15 | PRI_14 | PRI_13 | PRI_12 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_15 | R/W | 0h | Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). |
| 23-16 | PRI_14 | R/W | 0h | Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). |
| 15-8 | PRI_13 | R/W | 0h | Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). |
| 7-0 | PRI_12 | R/W | 0h | Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). |
NVIC_IPR4 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR4_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR4_TABLE.
Return to the Summary Table.
Irq 16 to 19 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_19 | PRI_18 | PRI_17 | PRI_16 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_19 | R/W | 0h | Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). |
| 23-16 | PRI_18 | R/W | 0h | Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). |
| 15-8 | PRI_17 | R/W | 0h | Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). |
| 7-0 | PRI_16 | R/W | 0h | Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). |
NVIC_IPR5 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR5_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR5_TABLE.
Return to the Summary Table.
Irq 20 to 23 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_23 | PRI_22 | PRI_21 | PRI_20 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_23 | R/W | 0h | Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). |
| 23-16 | PRI_22 | R/W | 0h | Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). |
| 15-8 | PRI_21 | R/W | 0h | Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). |
| 7-0 | PRI_20 | R/W | 0h | Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). |
NVIC_IPR6 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR6_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR6_TABLE.
Return to the Summary Table.
Irq 24 to 27 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_27 | PRI_26 | PRI_25 | PRI_24 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_27 | R/W | 0h | Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). |
| 23-16 | PRI_26 | R/W | 0h | Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). |
| 15-8 | PRI_25 | R/W | 0h | Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). |
| 7-0 | PRI_24 | R/W | 0h | Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). |
NVIC_IPR7 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR7_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR7_TABLE.
Return to the Summary Table.
Irq 28 to 31 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_31 | PRI_30 | PRI_29 | PRI_28 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_31 | R/W | 0h | Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). |
| 23-16 | PRI_30 | R/W | 0h | Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). |
| 15-8 | PRI_29 | R/W | 0h | Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). |
| 7-0 | PRI_28 | R/W | 0h | Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). |
NVIC_IPR8 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR8_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR8_TABLE.
Return to the Summary Table.
Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_35 | PRI_34 | PRI_33 | PRI_32 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_35 | R/W | 0h | Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). |
| 23-16 | PRI_34 | R/W | 0h | Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). |
| 15-8 | PRI_33 | R/W | 0h | Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). |
| 7-0 | PRI_32 | R/W | 0h | Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). |
NVIC_IPR9 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR9_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_NVIC_IPR9_TABLE.
Return to the Summary Table.
Irq 32 to 35 Priority
This register is used to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers changes based on the setting in AIRCR.PRIGROUP.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRI_37 | PRI_36 | |||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 15-8 | PRI_37 | R/W | 0h | Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). |
| 7-0 | PRI_36 | R/W | 0h | Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). |
CPUID is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPUID_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPUID_TABLE.
Return to the Summary Table.
CPUID Base
This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IMPLEMENTER | VARIANT | CONSTANT | |||||||||||||
| R-41h | R-0h | R-Fh | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PARTNO | REVISION | ||||||||||||||
| R-C24h | R-1h | ||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | IMPLEMENTER | R | 41h | Implementor code. |
| 23-20 | VARIANT | R | 0h | Implementation defined variant number. |
| 19-16 | CONSTANT | R | Fh | Reads as 0xF |
| 15-4 | PARTNO | R | C24h | Number of processor within family. |
| 3-0 | REVISION | R | 1h | Implementation defined revision number. |
ICSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ICSR_TABLE.
Return to the Summary Table.
Interrupt Control State
This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NMIPENDSET | RESERVED | PENDSVSET | PENDSVCLR | PENDSTSET | PENDSTCLR | RESERVED | |
| R/W-0h | R/W-0h | R/W-0h | W-X | R/W-0h | W-X | R-0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ISRPREEMPT | ISRPENDING | RESERVED | VECTPENDING | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| VECTPENDING | RETTOBASE | RESERVED | VECTACTIVE | ||||
| R-0h | R-0h | R-0h | R-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VECTACTIVE | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | NMIPENDSET | R/W | 0h | Set pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 0: No action 1: Set pending NMI |
| 30-29 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 28 | PENDSVSET | R/W | 0h | Set pending pendSV bit. 0: No action 1: Set pending PendSV |
| 27 | PENDSVCLR | W | X | Clear pending pendSV bit 0: No action 1: Clear pending pendSV |
| 26 | PENDSTSET | R/W | 0h | Set a pending SysTick bit. 0: No action 1: Set pending SysTick |
| 25 | PENDSTCLR | W | X | Clear pending SysTick bit 0: No action 1: Clear pending SysTick |
| 24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23 | ISRPREEMPT | R | 0h | This field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced. 0: A pending exception is not serviced. 1: A pending exception is serviced on exit from the debug halt state |
| 22 | ISRPENDING | R | 0h | Interrupt pending flag. Excludes NMI and faults. 0x0: Interrupt not pending 0x1: Interrupt pending |
| 21-18 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 17-12 | VECTPENDING | R | 0h | Pending ISR number field. This field contains the interrupt number of the highest priority pending ISR. |
| 11 | RETTOBASE | R | 0h | Indicates whether there are preempted active exceptions: 0: There are preempted active exceptions to execute 1: There are no active exceptions, or the currently-executing exception is the only active exception. |
| 10-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 8-0 | VECTACTIVE | R | 0h | Active ISR number field. Reset clears this field. |
VTOR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_VTOR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_VTOR_TABLE.
Return to the Summary Table.
Vector Table Offset
This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | TBLOFF | ||||||
| R/W-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TBLOFF | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TBLOFF | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TBLOFF | RESERVED | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 29-7 | TBLOFF | R/W | 0h | Bits 29 down to 7 of the vector table base offset. |
| 6-0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
AIRCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AIRCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AIRCR_TABLE.
Return to the Summary Table.
Application Interrupt/Reset Control
This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| VECTKEY | |||||||
| R/W-FA05h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| VECTKEY | |||||||
| R/W-FA05h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ENDIANESS | RESERVED | PRIGROUP | |||||
| R-0h | R-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SYSRESETREQ | VECTCLRACTIVE | VECTRESET | ||||
| R/W-0h | W-0h | W-0h | W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | VECTKEY | R/W | FA05h | Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05. |
| 15 | ENDIANESS | R | 0h | Data endianness bit
0h = Little endian 1h = Big endian |
| 14-11 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 10-8 | PRIGROUP | R/W | 0h | Interrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. |
| 7-3 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | SYSRESETREQ | W | 0h | Requests a warm reset. Setting this bit does not prevent Halting Debug from running. |
| 1 | VECTCLRACTIVE | W | 0h | Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set. |
| 0 | VECTRESET | W | 0h | System Reset bit. Resets the system, with the exception of debug components. This bit is reserved for debug use and can be written to 1 only when the core is halted. The bit self-clears. Writing this bit to 1 while core is not halted may result in unpredictable behavior. |
SCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SCR_TABLE.
Return to the Summary Table.
System Control
This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SEVONPEND | RESERVED | SLEEPDEEP | SLEEPONEXIT | RESERVED | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 4 | SEVONPEND | R/W | 0h | Send Event on Pending bit: 0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction. |
| 3 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | SLEEPDEEP | R/W | 0h | Controls whether the processor uses sleep or deep sleep as its low power mode
0h = Sleep 1h = Deep sleep |
| 1 | SLEEPONEXIT | R/W | 0h | Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 0: Do not sleep when returning to thread mode 1: Sleep on ISR exit |
| 0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
CCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CCR_TABLE.
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Configuration Control
This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | STKALIGN | BFHFNMIGN | |||||
| R/W-0h | R/W-1h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DIV_0_TRP | UNALIGN_TRP | RESERVED | USERSETMPEND | NONBASETHREDENA | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 9 | STKALIGN | R/W | 1h | Stack alignment bit. 0: Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 1: On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. |
| 8 | BFHFNMIGN | R/W | 0h | Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers: 0: Data BusFaults caused by load and store instructions cause a lock-up 1: Data BusFaults caused by load and store instructions are ignored. Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect problems. |
| 7-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 4 | DIV_0_TRP | R/W | 0h | Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0. 1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO. |
| 3 | UNALIGN_TRP | R/W | 0h | Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED. If this bit is set to 1, an unaligned access generates a UsageFault. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP. |
| 2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 1 | USERSETMPEND | R/W | 0h | Enables unprivileged software access to STIR: 0: User code is not allowed to write to the Software Trigger Interrupt register (STIR). 1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer. |
| 0 | NONBASETHREDENA | R/W | 0h | Indicates how the processor enters Thread mode: 0: Processor can enter Thread mode only when no exception is active. 1: Processor can enter Thread mode from any level using the appropriate return value (EXC_RETURN). Exception returns occur when one of the following instructions loads a value of 0xFXXXXXXX into the PC while in Handler mode: - POP/LDM which includes loading the PC. - LDR with PC as a destination. - BX with any register. The value written to the PC is intercepted and is referred to as the EXC_RETURN value. |
SHPR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR1_TABLE.
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System Handlers 4-7 Priority
This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRI_6 | PRI_5 | PRI_4 | ||||||||||||||||||||||||||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-16 | PRI_6 | R/W | 0h | Priority of system handler 6. UsageFault |
| 15-8 | PRI_5 | R/W | 0h | Priority of system handler 5: BusFault |
| 7-0 | PRI_4 | R/W | 0h | Priority of system handler 4: MemManage |
SHPR2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR2_TABLE.
Return to the Summary Table.
System Handlers 8-11 Priority
This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_11 | RESERVED | ||||||||||||||||||||||||||||||
| R/W-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_11 | R/W | 0h | Priority of system handler 11. SVCall |
| 23-0 | RESERVED | R | 0h | Reserved |
SHPR3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHPR3_TABLE.
Return to the Summary Table.
System Handlers 12-15 Priority
This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PRI_15 | PRI_14 | RESERVED | PRI_12 | ||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | R-0h | R/W-0h | ||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PRI_15 | R/W | 0h | Priority of system handler 15. SysTick exception |
| 23-16 | PRI_14 | R/W | 0h | Priority of system handler 14. Pend SV |
| 15-8 | RESERVED | R | 0h | Reserved |
| 7-0 | PRI_12 | R/W | 0h | Priority of system handler 12. Debug Monitor |
SHCSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHCSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_SHCSR_TABLE.
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System Handler Control and State
This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | USGFAULTENA | BUSFAULTENA | MEMFAULTENA | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SVCALLPENDED | BUSFAULTPENDED | MEMFAULTPENDED | USGFAULTPENDED | SYSTICKACT | PENDSVACT | RESERVED | MONITORACT |
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SVCALLACT | RESERVED | USGFAULTACT | RESERVED | BUSFAULTACT | MEMFAULTACT | ||
| R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 18 | USGFAULTENA | R/W | 0h | Usage fault system handler enable
0h = Exception disabled 1h = Exception enabled |
| 17 | BUSFAULTENA | R/W | 0h | Bus fault system handler enable
0h = Exception disabled 1h = Exception enabled |
| 16 | MEMFAULTENA | R/W | 0h | MemManage fault system handler enable
0h = Exception disabled 1h = Exception enabled |
| 15 | SVCALLPENDED | R | 0h | SVCall pending
0h = Exception is not active 1h = Exception is pending. |
| 14 | BUSFAULTPENDED | R | 0h | BusFault pending
0h = Exception is not active 1h = Exception is pending. |
| 13 | MEMFAULTPENDED | R | 0h | MemManage exception pending
0h = Exception is not active 1h = Exception is pending. |
| 12 | USGFAULTPENDED | R | 0h | Usage fault pending
0h = Exception is not active 1h = Exception is pending. |
| 11 | SYSTICKACT | R | 0h | SysTick active flag. 0x0: Not active 0x1: Active 0h = Exception is not active 1h = Exception is active |
| 10 | PENDSVACT | R | 0h | PendSV active 0x0: Not active 0x1: Active |
| 9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 8 | MONITORACT | R | 0h | Debug monitor active
0h = Exception is not active 1h = Exception is active |
| 7 | SVCALLACT | R | 0h | SVCall active
0h = Exception is not active 1h = Exception is active |
| 6-4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3 | USGFAULTACT | R | 0h | UsageFault exception active
0h = Exception is not active 1h = Exception is active |
| 2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 1 | BUSFAULTACT | R | 0h | BusFault exception active
0h = Exception is not active 1h = Exception is active |
| 0 | MEMFAULTACT | R | 0h | MemManage exception active
0h = Exception is not active 1h = Exception is active |
CFSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CFSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CFSR_TABLE.
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Configurable Fault Status
This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows:
The following accesses are possible to the CFSR register:
- access the complete register with a word access to 0xE000ED28.
- access the MMFSR with a byte access to 0xE000ED28
- access the MMFSR and BFSR with a halfword access to 0xE000ED28
- access the BFSR with a byte access to 0xE000ED29
- access the UFSR with a halfword access to 0xE000ED2A.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | DIVBYZERO | UNALIGNED | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | NOCP | INVPC | INVSTATE | UNDEFINSTR | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| BFARVALID | RESERVED | STKERR | UNSTKERR | IMPRECISERR | PRECISERR | IBUSERR | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MMARVALID | RESERVED | MSTKERR | MUNSTKERR | RESERVED | DACCVIOL | IACCVIOL | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 25 | DIVBYZERO | R/W | 0h | When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. |
| 24 | UNALIGNED | R/W | 0h | When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. |
| 23-20 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 19 | NOCP | R/W | 0h | Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions. |
| 18 | INVPC | R/W | 0h | Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC. |
| 17 | INVSTATE | R/W | 0h | Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state. |
| 16 | UNDEFINSTR | R/W | 0h | This bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction. |
| 15 | BFARVALID | R/W | 0h | This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten. |
| 14-13 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 12 | STKERR | R/W | 0h | Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written. |
| 11 | UNSTKERR | R/W | 0h | Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written. |
| 10 | IMPRECISERR | R/W | 0h | Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written. |
| 9 | PRECISERR | R/W | 0h | Precise data bus error return. |
| 8 | IBUSERR | R/W | 0h | Instruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written. |
| 7 | MMARVALID | R/W | 0h | Memory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten. |
| 6-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 4 | MSTKERR | R/W | 0h | Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written. |
| 3 | MUNSTKERR | R/W | 0h | Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written. |
| 2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 1 | DACCVIOL | R/W | 0h | Data access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access. |
| 0 | IACCVIOL | R/W | 0h | Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written. |
HFSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_HFSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_HFSR_TABLE.
Return to the Summary Table.
Hard Fault Status
This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DEBUGEVT | FORCED | RESERVED | |||||
| R/W1C-0h | R/W1C-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VECTTBL | RESERVED | |||||
| R/W-0h | R/W1C-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | DEBUGEVT | R/W1C | 0h | This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. |
| 30 | FORCED | R/W1C | 0h | Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. |
| 29-2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 1 | VECTTBL | R/W1C | 0h | This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. |
| 0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
DFSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DFSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DFSR_TABLE.
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Debug Fault Status
This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | EXTERNAL | VCATCH | DWTTRAP | BKPT | HALTED | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-5 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 4 | EXTERNAL | R/W | 0h | External debug request flag. The processor stops on next instruction boundary. 0x0: External debug request signal not asserted 0x1: External debug request signal asserted |
| 3 | VCATCH | R/W | 0h | Vector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault. 0x0: No vector catch occurred 0x1: Vector catch occurred |
| 2 | DWTTRAP | R/W | 0h | Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction. 0x0: No DWT match 0x1: DWT match |
| 1 | BKPT | R/W | 0h | BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 0x0: No BKPT instruction execution 0x1: BKPT instruction execution |
| 0 | HALTED | R/W | 0h | Halt request flag. The processor is halted on the next instruction. 0x0: No halt request 0x1: Halt requested by NVIC, including step |
MMFAR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MMFAR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MMFAR_TABLE.
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Mem Manage Fault Address
This register is used to read the address of the location that caused a Memory Manage Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDRESS | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | ADDRESS | R/W | X | Mem Manage fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault. |
BFAR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_BFAR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_BFAR_TABLE.
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Bus Fault Address
This register is used to read the address of the location that generated a Bus Fault.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDRESS | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | ADDRESS | R/W | X | Bus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault. |
AFSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AFSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_AFSR_TABLE.
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Auxiliary Fault Status
This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPDEF | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | IMPDEF | R/W | 0h | Implementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0 |
ID_PFR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR0_TABLE.
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Processor Feature 0
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0h | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | STATE1 | STATE0 | |||||||||||||
| R-0h | R-3h | R-0h | |||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-4 | STATE1 | R | 3h | State1 (T-bit == 1) 0x0: N/A 0x1: N/A 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.) 0x3: Thumb-2 encoding with all Thumb-2 basic instructions |
| 3-0 | STATE0 | R | 0h | State0 (T-bit == 0) 0x0: No ARM encoding 0x1: N/A |
ID_PFR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_PFR1_TABLE.
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Processor Feature 1
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MICROCONTROLLER_PROGRAMMERS_MODEL | ||||||
| R-0h | R-2h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 11-8 | MICROCONTROLLER_PROGRAMMERS_MODEL | R | 2h | Microcontroller programmer's model 0x0: Not supported 0x2: Two-stack support |
| 7-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_DFR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_DFR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_DFR0_TABLE.
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Debug Feature 0
This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MICROCONTROLLER_DEBUG_MODEL | RESERVED | ||||||
| R-1h | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 23-20 | MICROCONTROLLER_DEBUG_MODEL | R | 1h | Microcontroller Debug Model - memory mapped 0x0: Not supported 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) |
| 19-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_AFR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_AFR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_AFR0_TABLE.
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Auxiliary Feature 0
This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_MMFR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR0_TABLE.
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Memory Model Feature 0
General information on the memory model and memory management support.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-00100030h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 00100030h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_MMFR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR1_TABLE.
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Memory Model Feature 1
General information on the memory model and memory management support.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_MMFR2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR2_TABLE.
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Memory Model Feature 2
General information on the memory model and memory management support.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | WAIT_FOR_INTERRUPT_STALLING | ||||||
| R-0h | R-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | WAIT_FOR_INTERRUPT_STALLING | R | 1h | wait for interrupt stalling 0x0: Not supported 0x1: Wait for interrupt supported |
| 23-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_MMFR3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_MMFR3_TABLE.
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Memory Model Feature 3
General information on the memory model and memory management support.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_ISAR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR0_TABLE.
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ISA Feature 0
Information on the instruction set attributes register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-01101110h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 01101110h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_ISAR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR1_TABLE.
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ISA Feature 1
Information on the instruction set attributes register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-02112000h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 02112000h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_ISAR2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR2_TABLE.
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ISA Feature 2
Information on the instruction set attributes register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-21232231h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 21232231h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_ISAR3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR3_TABLE.
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ISA Feature 3
Information on the instruction set attributes register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-01111131h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 01111131h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ID_ISAR4 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR4_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_ID_ISAR4_TABLE.
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ISA Feature 4
Information on the instruction set attributes register
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R-01310132h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R | 01310132h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
CPACR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPACR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_CPACR_TABLE.
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Coprocessor Access Control
This register specifies the access privileges for coprocessors.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
MPU_TYPE is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_TYPE_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_TYPE_TABLE.
Return to the Summary Table.
MPU Type
This register indicates many regions the MPU supports.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| IREGION | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DREGION | |||||||
| R-8h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SEPARATE | ||||||
| R-0h | R-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reads 0. |
| 23-16 | IREGION | R | 0h | The processor core uses only a unified MPU, this field always reads 0x0. |
| 15-8 | DREGION | R | 8h | Number of supported MPU regions field. This field reads 0x08 indicating eight MPU regions. |
| 7-1 | RESERVED | R | 0h | Reads 0. |
| 0 | SEPARATE | R | 0h | The processor core uses only a unified MPU, thus this field is always 0. |
MPU_CTRL is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_CTRL_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_CTRL_TABLE.
Return to the Summary Table.
MPU Control
This register is used to enable the MPU, enable the default memory map (background region), and enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. When the MPU is enabled, at least one region of the memory map must be enabled for the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set and no regions are enabled, then only privileged code can operate. When the MPU is disabled, the default address map is used, as if no MPU is present. When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Unless HFNMIENA is set, the MPU is not enabled when the exception priority is -1 or -2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK is enabled. The HFNMIENA bit enables the MPU when operating with these two priorities.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PRIVDEFENA | HFNMIENA | ENABLE | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 2 | PRIVDEFENA | R/W | 0h | This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit is not set, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the system partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. |
| 1 | HFNMIENA | R/W | 0h | This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit and ENABLE are set, the MPU is enabled when in these handlers. If this bit is not set, the MPU is disabled when in these handlers, regardless of the value of ENABLE bit. If this bit is set and ENABLE is not set, behavior is unpredictable. |
| 0 | ENABLE | R/W | 0h | Enable MPU 0: MPU disabled 1: MPU enabled |
MPU_RNR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RNR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RNR_TABLE.
Return to the Summary Table.
MPU Region Number
This register is used to select which protection region is accessed. The following write to MPU_RASR or MPU_RBAR configures the characteristics of the protection region that is selected by this register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REGION | ||||||||||||||||||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-8 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 7-0 | REGION | R/W | 0h | Region select field. This field selects the region to operate on when using the MPU_RASR and MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID and MPU_RBAR.REGION fields are written, which overwrites this. |
MPU_RBAR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_TABLE.
Return to the Summary Table.
MPU Region Base Address
This register writes the base address of a region. It also contains a REGION field that can be used to override MPU_RNR.REGION, if the VALID bit is set. This register sets the base for the region. It is aligned by the size. So, a 64-KB sized region must be aligned on a multiple of 64KB, for example, 0x00010000 or 0x00020000. The region always reads back as the current MPU region number. VALID always reads back as 0. Writing VALID = 1 and REGION = n changes the region number to n. This is a short-hand way to write the MPU_RNR. This register is unpredictable if accessed other than as a word.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDR | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDR | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDR | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR | VALID | REGION | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-5 | ADDR | R/W | 0h | Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used. |
| 4 | VALID | R/W | 0h | MPU region number valid: 0: MPU_RNR remains unchanged and is interpreted. 1: MPU_RNR is overwritten by REGION. |
| 3-0 | REGION | R/W | 0h | MPU region override field |
MPU_RASR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_TABLE.
Return to the Summary Table.
MPU Region Attribute and Size
This register controls the MPU access permissions. The register is made up of two part registers, each of halfword size. These can be accessed using the halfword size, or they can both be simultaneously accessed using a word operation. The sub-region disable bits are not supported for region sizes of 32 bytes, 64 bytes, and 128 bytes. When these region sizes are used, the subregion disable bits must be programmed as 0.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | XN | RESERVED | AP | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TEX | S | C | B | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SRD | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SIZE | ENABLE | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 28 | XN | R/W | 0h | Instruction access disable: 0: Enable instruction fetches 1: Disable instruction fetches |
| 27 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 26-24 | AP | R/W | 0h | Data access permission: 0x0: Priviliged permissions: No access. User permissions: No access. 0x1: Priviliged permissions: Read-write. User permissions: No access. 0x2: Priviliged permissions: Read-write. User permissions: Read-only. 0x3: Priviliged permissions: Read-write. User permissions: Read-write. 0x4: Reserved 0x5: Priviliged permissions: Read-only. User permissions: No access. 0x6: Priviliged permissions: Read-only. User permissions: Read-only. 0x7: Priviliged permissions: Read-only. User permissions: Read-only. |
| 23-22 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 21-19 | TEX | R/W | 0h | Type extension |
| 18 | S | R/W | 0h | Shareable bit: 0: Not shareable 1: Shareable |
| 17 | C | R/W | 0h | Cacheable bit: 0: Not cacheable 1: Cacheable |
| 16 | B | R/W | 0h | Bufferable bit: 0: Not bufferable 1: Bufferable |
| 15-8 | SRD | R/W | 0h | Sub-Region Disable field: Setting a bit in this field disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less. |
| 7-6 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5-1 | SIZE | R/W | 0h | MPU Protection Region Size Field: 0x04: 32B 0x05: 64B 0x06: 128B 0x07: 256B 0x08: 512B 0x09: 1KB 0x0A: 2KB 0x0B: 4KB 0x0C: 8KB 0x0D: 16KB 0x0E: 32KB 0x0F: 64KB 0x10: 128KB 0x11: 256KB 0x12: 512KB 0x13: 1MB 0x14: 2MB 0x15: 4MB 0x16: 8MB 0x17: 16MB 0x18: 32MB 0x19: 64MB 0x1A: 128MB 0x1B: 256MB 0x1C: 512MB 0x1D: 1GB 0x1E: 2GB 0x1F: 4GB |
| 0 | ENABLE | R/W | 0h | Region enable bit: 0: Disable region 1: Enable region |
MPU_RBAR_A1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A1_TABLE.
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MPU Alias 1 Region Base Address
Alias for MPU_RBAR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RBAR_A1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RBAR_A1 | R/W | 0h | Alias for MPU_RBAR |
MPU_RASR_A1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A1_TABLE.
Return to the Summary Table.
MPU Alias 1 Region Attribute and Size
Alias for MPU_RASR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RASR_A1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RASR_A1 | R/W | 0h | Alias for MPU_RASR |
MPU_RBAR_A2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A2_TABLE.
Return to the Summary Table.
MPU Alias 2 Region Base Address
Alias for MPU_RBAR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RBAR_A2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RBAR_A2 | R/W | 0h | Alias for MPU_RBAR |
MPU_RASR_A2 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A2_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A2_TABLE.
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MPU Alias 2 Region Attribute and Size
Alias for MPU_RASR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RASR_A2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RASR_A2 | R/W | 0h | Alias for MPU_RASR |
MPU_RBAR_A3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RBAR_A3_TABLE.
Return to the Summary Table.
MPU Alias 3 Region Base Address
Alias for MPU_RBAR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RBAR_A3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RBAR_A3 | R/W | 0h | Alias for MPU_RBAR |
MPU_RASR_A3 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A3_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MPU_RASR_A3_TABLE.
Return to the Summary Table.
MPU Alias 3 Region Attribute and Size
Alias for MPU_RASR
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MPU_RASR_A3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | MPU_RASR_A3 | R/W | 0h | Alias for MPU_RASR |
DHCSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DHCSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DHCSR_TABLE.
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Debug Halting Control and Status
The purpose of this register is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to higher half-word of this register, otherwise the write operation is ignored and no bits are written into the register. If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled. This register is not reset on a core reset. It is reset by a power-on reset. However, C_HALT always clears on a core reset. To halt on a reset, the following bits must be enabled: DEMCR.VC_CORERESET and C_DEBUGEN. Note that writes to this register in any size other than word are unpredictable. It is acceptable to read in any size, and it can be used to avoid or intentionally change a sticky bit.
Behavior of the system when writing to this register while CPU is halted (i.e. C_DEBUGEN = 1 and S_HALT= 1):
C_HALT=0, C_STEP=0, C_MASKINTS=0 Exit Debug state and start instruction execution. Exceptions activate according to the exception configuration rules.
C_HALT=0, C_STEP=0, C_MASKINTS=1 Exit Debug state and start instruction execution. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=0 Exit Debug state, step an instruction and halt. Exceptions activate according to the exception configuration rules.
C_HALT=0, C_STEP=1, C_MASKINTS=1 Exit Debug state, step an instruction and halt. PendSV, SysTick and external configurable interrupts are disabled, otherwise exceptions activate according to standard configuration rules.
C_HALT=1, C_STEP=x, C_MASKINTS=x Remain in Debug state
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | S_RESET_ST | S_RETIRE_ST | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | S_LOCKUP | S_SLEEP | S_HALT | S_REGRDY | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-X | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | C_SNAPSTALL | RESERVED | C_MASKINTS | C_STEP | C_HALT | C_DEBUGEN | |
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. When writing to this register, 0x28 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 25 | S_RESET_ST | R/W | 0h | Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still). When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 24 | S_RETIRE_ST | R/W | 0h | Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch. When writing to this register, 0 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 23-20 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. When writing to this register, 0x5 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 19 | S_LOCKUP | R/W | 0h | Reads as one if the core is running (not halted) and a lockup condition is present. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 18 | S_SLEEP | R/W | 0h | Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must use C_HALT to gain control or wait for interrupt to wake-up. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 17 | S_HALT | R/W | 0h | The core is in debug state when this bit is set. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 16 | S_REGRDY | R/W | X | Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete. When writing to this register, 1 must be written this bit-field, otherwise the write operation is ignored and no bits are written into the register. |
| 15-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 5 | C_SNAPSTALL | R/W | 0h | If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE_ST can detect core stalls on load/store operations. |
| 4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 3 | C_MASKINTS | R/W | 0h | Mask interrupts when stepping or running in halted debug. This masking does not affect NMI, fault exceptions and SVC caused by execution of the instructions. This bit must only be modified when the processor is halted (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate). Modifying C_MASKINTS while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. |
| 2 | C_STEP | R/W | 0h | Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1). Modifying C_STEP while the system is running with halting debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. |
| 1 | C_HALT | R/W | 0h | Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. |
| 0 | C_DEBUGEN | R/W | 0h | Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself. The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will be unknown to software when C_DEBUGEN = 0. |
DCRSR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRSR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRSR_TABLE.
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Deubg Core Register Selector
The purpose of this register is to select the processor register to transfer data to or from. This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, DHCSR.S_REGRDY is 0. Note that writes to this register in any size but word are Unpredictable.
Note that PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions. Note that all bits can be written, but some combinations cause a fault when execution is resumed.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | REGWNR | ||||||
| W-X | W-X | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | REGSEL | ||||||
| W-X | W-X | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | W | X | Software should not rely on the value of a reserved. Write 0. |
| 16 | REGWNR | W | X | 1: Write 0: Read |
| 15-5 | RESERVED | W | X | Software should not rely on the value of a reserved. Write 0. |
| 4-0 | REGSEL | W | X | Register select 0x00: R0 0x01: R1 0x02: R2 0x03: R3 0x04: R4 0x05: R5 0x06: R6 0x07: R7 0x08: R8 0x09: R9 0x0A: R10 0x0B: R11 0x0C: R12 0x0D: Current SP 0x0E: LR 0x0F: DebugReturnAddress 0x10: XPSR/flags, execution state information, and exception number 0x11: MSP (Main SP) 0x12: PSP (Process SP) 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK |
DCRDR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRDR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DCRDR_TABLE.
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Debug Core Register Data
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DCRDR | |||||||||||||||||||||||||||||||
| R/W-X | |||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | DCRDR | R/W | X | This register holds data for reading and writing registers to and from the processor. This is the data value written to the register selected by DCRSR. When the processor receives a request from DCRSR, this register is read or written by the processor using a normal load-store unit operation. If core register transfers are not being performed, software-based debug monitors can use this register for communication in non-halting debug. This enables flags and bits to acknowledge state and indicate if commands have been accepted to, replied to, or accepted and replied to. |
DEMCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DEMCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_DEMCR_TABLE.
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Debug Exception and Monitor Control
The purpose of this register is vector catching and debug monitor control. This register manages exception behavior under debug. Vector catching is only available to halting debug. The upper halfword is for monitor controls and the lower halfword is for halting exception support. This register is not reset on a system reset. This register is reset by a power-on reset. The fields MON_EN, MON_PEND, MON_STEP and MON_REQ are always cleared on a core reset. The debug monitor is enabled by software in the reset handler or later, or by the **AHB-AP** port. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during a vector read or stack push error the halt occurs on the corresponding fault handler for the vector error or stack push. 2. If a late arriving interrupt detected during a vector read or stack push error it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | TRCENA | ||||||
| R/W-0h | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MON_REQ | MON_STEP | MON_PEND | MON_EN | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | VC_HARDERR | VC_INTERR | VC_BUSERR | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| VC_STATERR | VC_CHKERR | VC_NOCPERR | VC_MMERR | RESERVED | VC_CORERESET | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 24 | TRCENA | R/W | 0h | This bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. |
| 23-20 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 19 | MON_REQ | R/W | 0h | This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 0x0: Woken up by debug exception. 0x1: Woken up by MON_PEND |
| 18 | MON_STEP | R/W | 0h | When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI. |
| 17 | MON_PEND | R/W | 0h | Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor. |
| 16 | MON_EN | R/W | 0h | Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case. |
| 15-11 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 10 | VC_HARDERR | R/W | 0h | Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 9 | VC_INTERR | R/W | 0h | Debug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 8 | VC_BUSERR | R/W | 0h | Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 7 | VC_STATERR | R/W | 0h | Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 6 | VC_CHKERR | R/W | 0h | Debug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 5 | VC_NOCPERR | R/W | 0h | Debug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 4 | VC_MMERR | R/W | 0h | Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared. |
| 3-1 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 0 | VC_CORERESET | R/W | 0h | Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared. |
STIR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STIR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_STIR_TABLE.
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Software Trigger Interrupt
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INTID | ||||||||||||||||||||||||||||||
| W-0h | W-X | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | W | 0h | Software should not rely on the value of a reserved. Write 0. |
| 8-0 | INTID | W | X | Interrupt ID field. Writing a value to this bit-field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. |
FPCCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPCCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPCCR_TABLE.
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Floating Point Context Control
This register holds control data for the floating-point unit. Accessible only by privileged software.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ASPEN | LSPEN | RESERVED | |||||
| R/W-1h | R/W-1h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MONRDY | ||||||
| R/W-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | BFRDY | MMRDY | HFRDY | THREAD | RESERVED | USER | LSPACT |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | ASPEN | R/W | 1h | Automatic State Preservation enable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry. |
| 30 | LSPEN | R/W | 1h | Lazy State Preservation enable. Lazy state preservation is when the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation. 0: Disable automatic lazy state preservation for floating-point context. 1: Enable automatic lazy state preservation for floating-point context. |
| 29-9 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 8 | MONRDY | R/W | 0h | Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending. 0: DebugMonitor is disabled or priority did not permit setting DEMCR.MON_PEND when the floating-point stack frame was allocated. 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when the floating-point stack frame was allocated. |
| 7 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 6 | BFRDY | R/W | 0h | Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending. 0: BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 1: BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. |
| 5 | MMRDY | R/W | 0h | Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending. 0: MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 1: MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. |
| 4 | HFRDY | R/W | 0h | Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending. 0: Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 1: Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. |
| 3 | THREAD | R/W | 0h | Indicates the processor mode was Thread when it allocated the FP stack frame. 0: Mode was not Thread Mode when the floating-point stack frame was allocated. 1: Mode was Thread Mode when the floating-point stack frame was allocated. |
| 2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 1 | USER | R/W | 0h | Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame: 0: Privilege level was not user when the floating-point stack frame was allocated. 1: Privilege level was user when the floating-point stack frame was allocated. |
| 0 | LSPACT | R/W | 0h | Indicates whether Lazy preservation of the FP state is active: 0: Lazy state preservation is not active. 1: Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. |
FPCAR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPCAR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPCAR_TABLE.
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Floating-Point Context Address
This register holds the location of the unpopulated floating-point register space allocated on an exception stack frame.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ADDRESS | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ADDRESS | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ADDRESS | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDRESS | RESERVED | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | ADDRESS | R/W | 0h | Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame. |
| 1-0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
FPDSCR is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPDSCR_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_FPDSCR_TABLE.
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Floating Point Default Status Control
This register holds the default values for the floating-point status control data that the processor assigns to the FPSCR when it creates a new floating-point context. Accessible only by privileged software.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | AHP | DN | FZ | RMODE | RESERVED | ||||||||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||||||||||
| R/W-0h | |||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 26 | AHP | R/W | 0h | Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected). |
| 25 | DN | R/W | 0h | Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN). |
| 24 | FZ | R/W | 0h | Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled). |
| 23-22 | RMODE | R/W | 0h | Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode 0b01 Round towards Plus Infinity (RP) mode 0b10 Round towards Minus Infinity (RM) mode 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions). |
| 21-0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
MVFR0 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MVFR0_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MVFR0_TABLE.
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Media and FP Feature 0
Describes the features provided by the Floating-point extension.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FP_ROUNDING_MODES | SHORT_VECTORS | ||||||
| R-1h | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SQUARE_ROOT | DIVIDE | ||||||
| R-1h | R-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FP_EXCEPTION_TRAPPING | DOUBLE_PRECISION | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SINGLE_PRECISION | A_SIMD | ||||||
| R-2h | R-1h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | FP_ROUNDING_MODES | R | 1h | Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported. |
| 27-24 | SHORT_VECTORS | R | 0h | Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported. |
| 23-20 | SQUARE_ROOT | R | 1h | Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported. |
| 19-16 | DIVIDE | R | 1h | Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported. |
| 15-12 | FP_EXCEPTION_TRAPPING | R | 0h | Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported. |
| 11-8 | DOUBLE_PRECISION | R | 0h | Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported. |
| 7-4 | SINGLE_PRECISION | R | 2h | Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported. |
| 3-0 | A_SIMD | R | 1h | Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers. |
MVFR1 is shown in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MVFR1_FIGURE and described in #CPU_SCS_CPU_SCS_MAP1_CPU_SCS_ALL_MVFR1_TABLE.
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Media and FP Feature 1
Describes the features provided by the Floating-point extension.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| FP_FUSED_MAC | FP_HPFP | RESERVED | |||||||||||||
| R-1h | R-1h | R-0h | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | D_NAN_MODE | FTZ_MODE | |||||||||||||
| R-0h | R-1h | R-1h | |||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | FP_FUSED_MAC | R | 1h | Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported. |
| 27-24 | FP_HPFP | R | 1h | Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported. |
| 23-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. |
| 7-4 | D_NAN_MODE | R | 1h | Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values. |
| 3-0 | FTZ_MODE | R | 1h | Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic. |