SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
#MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_TABLE_1 lists the memory-mapped registers for the MCU_SRAM_MMR registers. All register offset addresses not listed in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | PER_CTL | Parity Error Control | #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CTL |
| 4h | PER_CHK | Parity Error Check | #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CHK |
| 8h | PER_DBG | Parity Error Debug | #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_DBG |
| Ch | MEM_CTL | Memory Control | #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_MEM_CTL |
Complex bit access types are encoded to fit into small table cells. #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
PER_CTL is shown in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CTL_FIGURE and described in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CTL_TABLE.
Return to the Summary Table.
Parity Error Control
Parity error check controls
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PER_DISABLE | ||||||
| R-0h | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PER_DEBUG_ENABLE | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R | 0h | Reserved |
| 8 | PER_DISABLE | R/W | 0h | Parity Status Disable 0: A parity error will update PER_CHK.PER_ADDR field 1: Parity error does not update PER_CHK.PER_ADDR field |
| 7-1 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
| 0 | PER_DEBUG_ENABLE | R/W | 0h | Parity Error Debug Enable 0: Normal operation 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity errors will be generated on reads from within this offset |
PER_CHK is shown in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CHK_FIGURE and described in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_CHK_TABLE.
Return to the Summary Table.
Parity Error Check
Parity error check results
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PER_ADDR | ||||||||||||||||||||||||||||||
| R-0h | R-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | PER_ADDR | R | 0h | Parity Error Address Offset Returns the last address offset which resulted in a parity error during an SRAM read. The address offset returned is always the word-aligned address that contains the location with the parity error. For parity faults on non word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the location that resulted in parity error. |
PER_DBG is shown in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_DBG_FIGURE and described in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_PER_DBG_TABLE.
Return to the Summary Table.
Parity Error Debug
Parity error check debug address setting
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PER_DEBUG_ADDR | ||||||||||||||||||||||||||||||
| R-0h | R/W-0h | ||||||||||||||||||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | 0h | Reserved |
| 23-0 | PER_DEBUG_ADDR | R/W | 0h | Debug Parity Error Address Offset When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug address offset. The address offset must be a word-aligned address. Writes within this address offset will force incorrect parity bits to be stored together with the data written. The following reads within this same address offset will thus result in parity errors to be generated. |
MEM_CTL is shown in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_MEM_CTL_FIGURE and described in #MCU_SRAM_MMR_MCU_SRAM_MMR_MAP_SRAM_MCU_SRAM_MMR_ALL_MEM_CTL_TABLE.
Return to the Summary Table.
Memory Control
Controls memory initialization
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MEM_BUSY | MEM_CLR_EN | |||||
| R-0h | R-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | 0h | Reserved |
| 1 | MEM_BUSY | R | 0h | Memory Busy status 0: Memory accepts transfers 1: Memory controller is busy during initialization. Read and write transfers are not performed. |
| 0 | MEM_CLR_EN | R/W | 0h | Memory Contents Initialization enable Writing 1 to MEM_CLR_EN will start memory initialization. The contents of all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until memory initialization has completed. |