SWCU192 User guide

SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7

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2. 9
3. 10
  1. 11
    1. 12
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    4. 15
  2. 16
    1. 17
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    3. 19
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    1. 23
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  6. 25
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    1. 28
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  13. 36
    1. 37
      1. 38
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43
1. 44
2. 45
3. 46
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4. 53
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5. 58
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    1. 61
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    21. 81
6. 82
  1. 83
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  3. 85
7. 86
  1. 87
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    1. 89
    2. 90
      1. 91
      2. 92
      3. 93
    3. 94
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    5. 96
    6. 97
      1. 98
      2. 99
      3. 100
    7. 101
  3. 102
    1. 103
      1. 104
8. 105
  1. 106
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  3. 108
9. 109
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115
1. 116
117
1. 118
2. 119
  1. 120
  2. 121
    1. 122
    2. 123
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  6. 127
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129
1. 130
  1. 131
  2. 132
  3. 133
  4. 134
  5. 135
  6. 136
  7. 137
    1. 138
    2. 139
2. 140
  1. 141
  2. 142
  3. 143
  4. 144
3. 145
  1. 146
  2. 147
    1. 148
4. 149
  1. 150
  2. 151
    1. 152
    2. 153
    3. 154
5. 155
  1. 156
  2. 157
    1. 158
    2. 159
    3. 160
6. 161
7. 162
  1. 163
  2. 164
165
1. 166
2. 167
  1. 168
    1. 169
  2. 170
    1. 171
    2. 172
    3. 173
3. 174
  1. 175
    1. 176
    2. 177
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    1. 179
    2. 180
    3. 181
    4. 182
    5. 183
    6. 184
    7. 185
    8. 186
  3. 187
  4. 188
    1. 189
      1. 190
      2. 191
      3. 192
    2. 193
      1. 194
    3. 195
      1. 196
4. 197
5. 198
6. 199
7. 200
8. 201
9. 202
10. 203
204
1. 205
2. 206
3. 207
  1. 208
4. 209
  1. 210
    1. 211
  2. 212
    1. 213
5. 214
  1. 215
    1. 216
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    1. 218
    2. 219
    3. 220
  3. 221
6. 222
  1. 223
  2. 224
  3. 225
  4. 226
  5. 227
7. 228
  1. 229
    1. 230
    2. 231
    3. 232
  2. 233
  3. 234
8. 235
  1. 236
  2. 237
  3. 238
239
1. 240
2. 241
  1. 242
    1. 243
    2. 244
    3. 245
  2. 246
  3. 247
  4. 248
3. 249
  1. 250
  2. 251
    1. 252
    2. 253
    3. 254
4. 255
5. 256
  1. 257
  2. 258
  3. 259
  4. 260
6. 261
7. 262
  1. 263
  2. 264
265
1. 266
2. 267
3. 268
4. 269
5. 270
6. 271
7. 272
  1. 273
  2. 274
275
1. 276
  1. 277
  2. 278
2. 279
  1. 280
    1. 281
  2. 282
    1. 283
      1. 284
    2. 285
  3. 286
    1. 287
    2. 288
    3. 289
    4. 290
    5. 291
    6. 292
    7. 293
    8. 294
    9. 295
    10. 296
    11. 297
    12. 298
    13. 299
300
1. 301
2. 302
  1. 303
3. 304
4. 305
  1. 306
307
1. 308
2. 309
  1. 310
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3. 312
4. 313
  1. 314
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  3. 316
5. 317
  1. 318
  2. 319
  3. 320
    1. 321
    2. 322
  4. 323
    1. 324
      1. 325
    2. 326
      1. 327
    3. 328
  5. 329
    1. 330
    2. 331
    3. 332
    4. 333
    5. 334
  6. 335
    1. 336
    2. 337
    3. 338
    4. 339
    5. 340
6. 341
  1. 342
  2. 343
7. 344
  1. 345
  2. 346
    1. 347
    2. 348
    3. 349
  3. 350
    1. 351
    2. 352
      1. 353
      2. 354
      3. 355
    3. 356
      1. 357
    4. 358
      1. 359
      2. 360
  4. 361
    1. 362
    2. 363
      1. 364
    3. 365
      1. 366
      2. 367
      3. 368
      4. 369
    4. 370
      1. 371
    5. 372
      1. 373
    6. 374
      1. 375
  5. 376
    1. 377
    2. 378
    3. 379
      1. 380
      2. 381
        
        382
      3.        383
        
                384
        
                385
        
                 386
        
                 387
        
                 388
        
                 389
        
                 390
        
                 391
        
                 392
        
                 393
        
                394
        
                395
        
                396
8. 397
  1. 398
    1. 399
    2. 400
  2. 401
9. 402
  1. 403
404
1. 405
2. 406
3. 407
  1. 408
  2. 409
  3. 410
  4. 411
4. 412
  1. 413
5. 414
6. 415
7. 416
8. 417
9. 418
  1. 419
    1. 420
    2. 421
10. 422
  1. 423
  2. 424
  3. 425
426
1. 427
2. 428
3. 429
  1. 430
  2. 431
  3. 432
  4. 433
    1. 434
    2. 435
  5. 436
  6. 437
    1. 438
    2. 439
    3. 440
    4. 441
    5. 442
    6. 443
  7. 444
  8. 445
  9. 446
  10. 447
4. 448
  1. 449
  2. 450
    1. 451
    2. 452
    3. 453
5. 454
  1. 455
456
1. 457
2. 458
3. 459
  1. 460
  2. 461
    1. 462
    2. 463
    3. 464
    4. 465
    5. 466
  3. 467
  4. 468
4. 469
  1. 470
  2. 471
  3. 472
  4. 473
  5. 474
5. 475
  1. 476
477
1. 478
2. 479
  1. 480
  2. 481
  3. 482
    1. 483
  4. 484
3. 485
  1. 486
  2. 487
  3. 488
4. 489
  1. 490
491
1. 492
2. 493
3. 494
4. 495
  1. 496
497
1. 498
2. 499
3. 500
4. 501
5. 502
  1. 503
  2. 504
  3. 505
6. 506
  1. 507
    1. 508
    2. 509
    3. 510
      1. 511
      2. 512
7. 513
  1. 514
515
1. 516
  1. 517
2. 518
  1. 519
    1. 520
  2. 521
    1. 522
    2. 523
  3. 524
  4. 525
3. 526
  1. 527
    1. 528
    2. 529
    3. 530
    4. 531
  2. 532
    1. 533
      1. 534
    2. 535
      1. 536
      2. 537
    3. 538
      1. 539
    4. 540
      1. 541
      2. 542
      3. 543
    5. 544
    6. 545
    7. 546
    8. 547
    9. 548
    10. 549
4. 550
  1. 551
    1. 552
  2. 553
    1. 554
    2. 555
      1. 556
      2. 557
      3. 558
      4. 559
      5. 560
  3. 561
    1. 562
    2. 563
    3. 564
  4. 565
    1. 566
    2. 567
      1. 568
      2. 569
      3. 570
  5. 571
    1. 572
    2. 573
      1. 574
      2. 575
      3. 576
      4.        577
        
                578
        
                579
      5. 580
      6. 581
    3. 582
      1. 583
      2. 584
      3.        585
        
                586
        
                587
        
                588
        
                589
      4. 590
  6. 591
    1. 592
    2. 593
  7. 594
    1. 595
    2. 596
      1. 597
      2. 598
      3. 599
      4. 600
      5.        601
        
                602
        
                 603
        
                604
        
                 605
        
                606
        
                 607
      6. 608
5. 609
  1. 610
    1. 611
    2. 612
  2. 613
    1. 614
    2. 615
      1. 616
      2. 617
      3. 618
      4. 619
      5. 620
      6. 621
      7. 622
      8. 623
  3. 624
    1. 625
    2. 626
      1. 627
      2. 628
      3. 629
      4. 630
  4. 631
    1. 632
    2. 633
      1. 634
      2. 635
      3.        636
        
                637
        
                638
  5. 639
    1. 640
    2. 641
      1. 642
      2. 643
      3.        644
        
                645
        
                646
        
                647
      4.        648
        
                649
        
                650
        
                651
        
                652
      5. 653
      6. 654
  6. 655
    1. 656
    2. 657
      1. 658
      2. 659
      3. 660
      4. 661
      5. 662
6. 663
  1. 664
    1. 665
    2. 666
      1.        667
        
                668
        
                669
  2. 670
  3. 671
  4. 672
  5. 673
  6. 674
  7. 675
7. 676
8. 677
  1. 678
  2. 679
  3. 680
  4. 681
  5. 682
  6. 683
  7. 684
  8. 685
  9. 686
  10. 687
  11. 688
  12. 689
690
1. 691
2. 692
3. 693
  1. 694
695
1. 696
2. 697
3. 698
4. 699
  1. 700
  2. 701
  3. 702
  4. 703
    1. 704
    2. 705
      1. 706
      2. 707
  5. 708
  6. 709
  7. 710
5. 711
6. 712
7. 713
  1. 714
715
1. 716
2. 717
3. 718
4. 719
  1. 720
  2. 721
    1. 722
    2. 723
  3. 724
  4. 725
    1. 726
    2. 727
      1. 728
      2. 729
    3. 730
    4. 731
    5. 732
    6. 733
    7. 734
5. 735
6. 736
7. 737
  1. 738
739
1. 740
2. 741
3. 742
  1. 743
    1. 744
    2. 745
    3. 746
    4. 747
    5. 748
  2. 749
    1. 750
  3. 751
    1. 752
    2. 753
  4. 754
  5. 755
    1. 756
    2. 757
4. 758
5. 759
  1. 760
761
1. 762
2. 763
3. 764
4. 765
  1. 766
    1. 767
  2. 768
  3. 769
  4. 770
    1. 771
  5. 772
    1. 773
  6. 774
    1. 775
  7. 776
    1. 777
  8. 778
    1. 779
    2. 780
5. 781
  1. 782
  2. 783
  3. 784
  4. 785
    1. 786
    2. 787
    3. 788
6. 789
  1. 790
  2. 791
  3. 792
  4. 793
7. 794
8. 795
  1. 796
  2. 797
9. 798
  1. 799
800
1. 801
  1. 802
2. 803
  1. 804
  2. 805
  3. 806
    1. 807
    2. 808
    3. 809
  4. 810
    1. 811
    2. 812
    3. 813
3. 814
  1. 815
  2. 816
    1. 817
    2. 818
    3. 819
    4. 820
    5. 821
      1. 822
      2. 823
      3. 824
    6. 825
      1. 826
    7. 827
      1. 828
      2. 829
      3. 830
      4. 831
    8. 832
  3. 833
    1. 834
      1. 835
      2. 836
      3. 837
      4. 838
      5. 839
      6. 840
      7. 841
      8. 842
      9. 843
      10. 844
      11. 845
      12. 846
      13. 847
      14. 848
    2. 849
      1. 850
      2. 851
      3. 852
      4. 853
      5. 854
      6. 855
      7. 856
      8. 857
      9. 858
      10. 859
      11. 860
      12. 861
      13. 862
      14. 863
      15. 864
      16. 865
      17. 866
      18. 867
      19. 868
      20. 869
  4. 870
    1. 871
    2. 872
    3. 873
    4. 874
    5. 875
4. 876
  1. 877
    1. 878
    2. 879
    3. 880
    4. 881
    5. 882
  2. 883
    1. 884
    2. 885
5. 886
  1. 887
    1. 888
    2. 889
    3. 890
    4. 891
  2. 892
  3. 893
    1. 894
    2. 895
  4. 896
    1. 897
      1.        898
        
                899
        
                900
      2. 901
      3. 902
      4. 903
      5. 904
    2. 905
    3. 906
    4. 907
    5. 908
    6. 909
  5. 910
    1. 911
    2. 912
    3. 913
    4. 914
    5. 915
    6. 916
6. 917
  1. 918
    1. 919
      1. 920
    2. 921
    3. 922
    4. 923
  2. 924
7. 925
  1. 926
  2. 927
8. 928
  1. 929
  2. 930
  3. 931
  4. 932
  5. 933
  6. 934
  7. 935
  8. 936
    1. 937
    2. 938
    3. 939
    4. 940
  9. 941
    1. 942
    2. 943
    3. 944
  10. 945
    1. 946
    2. 947
    3. 948
    4. 949
    5. 950
  11. 951
    1. 952
    2. 953
    3. 954
    4. 955
    5. 956
  12. 957
  13. 958
  14. 959
  15. 960
  16. 961
  17. 962
9. 963
  1. 964
10. 965
  1. 966
  2. 967
    1. 968
      1. 969
    2. 970
    3. 971
  3. 972
  4. 973
    1. 974
    2. 975
  5. 976
    1. 977
    2. 978
      1. 979
    3. 980
      1. 981
      2. 982
    4. 983
      1. 984
      2. 985
    5. 986
      1. 987
      2. 988
      3. 989
  6. 990
    1. 991
    2. 992
11. 993
  1. 994
  2. 995
  3. 996
997

12.4.1 FCFG1 Registers

#FCFG1_FCFG1_MMAP1_TABLE_1 lists the memory-mapped registers for the FCFG1 registers. All register offset addresses not listed in #FCFG1_FCFG1_MMAP1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 12-25 FCFG1 Registers

Offset	Acronym	Register Name	Section
A0h	MISC_CONF_1	Misc configurations	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_1
A4h	MISC_CONF_2	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_2
C4h	CONFIG_CC26_FE	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC26_FE
C8h	CONFIG_CC13_FE	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC13_FE
CCh	CONFIG_RF_COMMON	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_RF_COMMON
D0h	CONFIG_SYNTH_DIV2_CC26_2G4	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_2G4
D4h	CONFIG_SYNTH_DIV2_CC13_2G4	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_2G4
D8h	CONFIG_SYNTH_DIV2_CC26_1G	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_1G
DCh	CONFIG_SYNTH_DIV2_CC13_1G	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_1G
E0h	CONFIG_SYNTH_DIV4_CC26	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC26
E4h	CONFIG_SYNTH_DIV4_CC13	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC13
E8h	CONFIG_SYNTH_DIV5	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV5
ECh	CONFIG_SYNTH_DIV6_CC26	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC26
F0h	CONFIG_SYNTH_DIV6_CC13	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC13
F4h	CONFIG_SYNTH_DIV10	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV10
F8h	CONFIG_SYNTH_DIV12_CC26	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC26
FCh	CONFIG_SYNTH_DIV12_CC13	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC13
100h	CONFIG_SYNTH_DIV15	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV15
104h	CONFIG_SYNTH_DIV30	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV30
164h	FLASH_NUMBER	Flash information	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_NUMBER
16Ch	FLASH_COORDINATE	Flash information	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_COORDINATE
170h	FLASH_E_P	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_E_P
174h	FLASH_C_E_P_R	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_C_E_P_R
178h	FLASH_P_R_PV	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_P_R_PV
17Ch	FLASH_EH_SEQ	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_EH_SEQ
180h	FLASH_VHV_E	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_E
184h	FLASH_PP	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PP
188h	FLASH_PROG_EP	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PROG_EP
18Ch	FLASH_ERA_PW	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_ERA_PW
190h	FLASH_VHV	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV
194h	FLASH_VHV_PV	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_PV
198h	FLASH_V	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_V
294h	USER_ID	User Identification.	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_USER_ID
2B0h	FLASH_OTP_DATA3	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA3
2B4h	ANA2_TRIM	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANA2_TRIM
2B8h	LDO_TRIM	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_LDO_TRIM
2E8h	MAC_BLE_0	MAC BLE Address 0	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_0
2ECh	MAC_BLE_1	MAC BLE Address 1	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_1
2F0h	MAC_15_4_0	MAC IEEE 802.15.4 Address 0	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_0
2F4h	MAC_15_4_1	MAC IEEE 802.15.4 Address 1	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_1
308h	FLASH_OTP_DATA4	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA4
30Ch	MISC_TRIM	Miscellaneous Trim Parameters	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_TRIM
310h	RCOSC_HF_TEMPCOMP	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_RCOSC_HF_TEMPCOMP
318h	ICEPICK_DEVICE_ID	IcePick Device Identification	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_ICEPICK_DEVICE_ID
31Ch	FCFG1_REVISION	Factory Configuration (FCFG1) Revision	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FCFG1_REVISION
320h	MISC_OTP_DATA	Misc OTP Data	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA
344h	IOCONF	IO Configuration	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_IOCONF
34Ch	CONFIG_IF_ADC	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_IF_ADC
350h	CONFIG_OSC_TOP	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_OSC_TOP
35Ch	SOC_ADC_ABS_GAIN	AUX_ADC Gain in Absolute Reference Mode	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_ABS_GAIN
360h	SOC_ADC_REL_GAIN	AUX_ADC Gain in Relative Reference Mode	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REL_GAIN
368h	SOC_ADC_OFFSET_INT	AUX_ADC Temperature Offsets in Absolute Reference Mode	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_OFFSET_INT
36Ch	SOC_ADC_REF_TRIM_AND_OFFSET_EXT	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REF_TRIM_AND_OFFSET_EXT
370h	AMPCOMP_TH1	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH1
374h	AMPCOMP_TH2	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH2
378h	AMPCOMP_CTRL1	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_CTRL1
37Ch	ANABYPASS_VALUE2	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANABYPASS_VALUE2
388h	VOLT_TRIM	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_VOLT_TRIM
38Ch	OSC_CONF	OSC Configuration	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_OSC_CONF
390h	FREQ_OFFSET	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_FREQ_OFFSET
398h	MISC_OTP_DATA_1	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA_1
3D0h	SHDW_DIE_ID_0	Shadow of EFUSE:DIE_ID_0 register	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_0
3D4h	SHDW_DIE_ID_1	Shadow of EFUSE:DIE_ID_1 register	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_1
3D8h	SHDW_DIE_ID_2	Shadow of EFUSE:DIE_ID_2 register	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_2
3DCh	SHDW_DIE_ID_3	Shadow of EFUSE:DIE_ID_3 register	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_3
3F8h	SHDW_OSC_BIAS_LDO_TRIM	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_OSC_BIAS_LDO_TRIM
3FCh	SHDW_ANA_TRIM	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_ANA_TRIM
40Ch	DAC_BIAS_CNF	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_BIAS_CNF
418h	TFW_PROBE	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_PROBE
41Ch	TFW_FT	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_FT
420h	DAC_CAL0	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL0
424h	DAC_CAL1	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL1
428h	DAC_CAL2	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL2
42Ch	DAC_CAL3	Internal	#FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL3

Complex bit access types are encoded to fit into small table cells. #FCFG1_FCFG1_MMAP1_LEGEND shows the codes that are used for access types in this section.

Table 12-26 FCFG1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Reset or Default Value
-n		Value after reset or the default value

12.4.1.1 MISC_CONF_1 Register (Offset = A0h) [Reset = X]

MISC_CONF_1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_1_TABLE.

Return to the Summary Table.

Misc configurations

Figure 12-23 MISC_CONF_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								DEVICE_MINOR_REV
R-0h								R-X

Table 12-27 MISC_CONF_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	DEVICE_MINOR_REV	R	X	HW minor revision number (a value of 0xFF shall be treated equally to 0x00). Any test of this field by SW should be implemented as a 'greater or equal' comparison as signed integer. Value may change without warning. Default value holds log information from production test.

12.4.1.2 MISC_CONF_2 Register (Offset = A4h) [Reset = X]

MISC_CONF_2 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_2_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_CONF_2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-24 MISC_CONF_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 12-28 MISC_CONF_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	0h	Reserved

12.4.1.3 CONFIG_CC26_FE Register (Offset = C4h) [Reset = X]

CONFIG_CC26_FE is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC26_FE_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC26_FE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-25 CONFIG_CC26_FE Register

31	30	29	28	27	26	25	24
IFAMP_IB				LNA_IB
R-7h				R-X

23	22	21	20	19	18	17	16
IFAMP_TRIM					CTL_PA0_TRIM
R-0h					R-X

15	14	13	12	11	10	9	8
CTL_PA0_TRIM		PATRIMCOMPLETE_N	RSSITRIMCOMPLETE_N	RESERVED
R-X		R-X	R-X	R-0h

7	6	5	4	3	2	1	0
RSSI_OFFSET
R-X

Table 12-29 CONFIG_CC26_FE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	IFAMP_IB	R	7h	Internal. Only to be used through TI provided API.
27-24	LNA_IB	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-19	IFAMP_TRIM	R	0h	Internal. Only to be used through TI provided API.
18-14	CTL_PA0_TRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
13	PATRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
12	RSSITRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-8	RESERVED	R	0h	Reserved
7-0	RSSI_OFFSET	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.4 CONFIG_CC13_FE Register (Offset = C8h) [Reset = X]

CONFIG_CC13_FE is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC13_FE_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_CC13_FE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-26 CONFIG_CC13_FE Register

31	30	29	28	27	26	25	24
IFAMP_IB				LNA_IB
R-7h				R-X

23	22	21	20	19	18	17	16
IFAMP_TRIM					CTL_PA0_TRIM
R-0h					R-X

15	14	13	12	11	10	9	8
CTL_PA0_TRIM		PATRIMCOMPLETE_N	RSSITRIMCOMPLETE_N	RESERVED
R-X		R-X	R-X	R-0h

7	6	5	4	3	2	1	0
RSSI_OFFSET
R-X

Table 12-30 CONFIG_CC13_FE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	IFAMP_IB	R	7h	Internal. Only to be used through TI provided API.
27-24	LNA_IB	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-19	IFAMP_TRIM	R	0h	Internal. Only to be used through TI provided API.
18-14	CTL_PA0_TRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
13	PATRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
12	RSSITRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-8	RESERVED	R	0h	Reserved
7-0	RSSI_OFFSET	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.5 CONFIG_RF_COMMON Register (Offset = CCh) [Reset = X]

CONFIG_RF_COMMON is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_RF_COMMON_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_RF_COMMON_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-27 CONFIG_RF_COMMON Register

31	30	29	28	27	26	25	24
DISABLE_CORNER_CAP	SLDO_TRIM_OUTPUT						RESERVED
R-1h	R-X						R-0h

23	22	21	20	19	18	17	16
RESERVED		PA20DBMTRIMCOMPLETE_N	CTL_PA_20DBM_TRIM
R-0h		R-X	R-X

15	14	13	12	11	10	9	8
RFLDO_TRIM_OUTPUT							QUANTCTLTHRES
R-X							R-5h

7	6	5	4	3	2	1	0
QUANTCTLTHRES		DACTRIM
R-5h		R-Dh

Table 12-31 CONFIG_RF_COMMON Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DISABLE_CORNER_CAP	R	1h	Internal. Only to be used through TI provided API.
30-25	SLDO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
24-22	RESERVED	R	0h	Reserved
21	PA20DBMTRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API.
20-16	CTL_PA_20DBM_TRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-9	RFLDO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API.
8-6	QUANTCTLTHRES	R	5h	Internal. Only to be used through TI provided API.
5-0	DACTRIM	R	Dh	Internal. Only to be used through TI provided API.

12.4.1.6 CONFIG_SYNTH_DIV2_CC26_2G4 Register (Offset = D0h) [Reset = X]

CONFIG_SYNTH_DIV2_CC26_2G4 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_2G4_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_2G4_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-28 CONFIG_SYNTH_DIV2_CC26_2G4 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-32 CONFIG_SYNTH_DIV2_CC26_2G4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.7 CONFIG_SYNTH_DIV2_CC13_2G4 Register (Offset = D4h) [Reset = X]

CONFIG_SYNTH_DIV2_CC13_2G4 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_2G4_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_2G4_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-29 CONFIG_SYNTH_DIV2_CC13_2G4 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-33 CONFIG_SYNTH_DIV2_CC13_2G4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.8 CONFIG_SYNTH_DIV2_CC26_1G Register (Offset = D8h) [Reset = X]

CONFIG_SYNTH_DIV2_CC26_1G is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_1G_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC26_1G_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-30 CONFIG_SYNTH_DIV2_CC26_1G Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-34 CONFIG_SYNTH_DIV2_CC26_1G Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.9 CONFIG_SYNTH_DIV2_CC13_1G Register (Offset = DCh) [Reset = X]

CONFIG_SYNTH_DIV2_CC13_1G is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_1G_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV2_CC13_1G_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-31 CONFIG_SYNTH_DIV2_CC13_1G Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-35 CONFIG_SYNTH_DIV2_CC13_1G Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.10 CONFIG_SYNTH_DIV4_CC26 Register (Offset = E0h) [Reset = X]

CONFIG_SYNTH_DIV4_CC26 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC26_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC26_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-32 CONFIG_SYNTH_DIV4_CC26 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-36 CONFIG_SYNTH_DIV4_CC26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.11 CONFIG_SYNTH_DIV4_CC13 Register (Offset = E4h) [Reset = X]

CONFIG_SYNTH_DIV4_CC13 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC13_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV4_CC13_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-33 CONFIG_SYNTH_DIV4_CC13 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-37 CONFIG_SYNTH_DIV4_CC13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.12 CONFIG_SYNTH_DIV5 Register (Offset = E8h) [Reset = X]

CONFIG_SYNTH_DIV5 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV5_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV5_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-34 CONFIG_SYNTH_DIV5 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-38 CONFIG_SYNTH_DIV5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.13 CONFIG_SYNTH_DIV6_CC26 Register (Offset = ECh) [Reset = X]

CONFIG_SYNTH_DIV6_CC26 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC26_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC26_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-35 CONFIG_SYNTH_DIV6_CC26 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-39 CONFIG_SYNTH_DIV6_CC26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.14 CONFIG_SYNTH_DIV6_CC13 Register (Offset = F0h) [Reset = X]

CONFIG_SYNTH_DIV6_CC13 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC13_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV6_CC13_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-36 CONFIG_SYNTH_DIV6_CC13 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-40 CONFIG_SYNTH_DIV6_CC13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.15 CONFIG_SYNTH_DIV10 Register (Offset = F4h) [Reset = X]

CONFIG_SYNTH_DIV10 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV10_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV10_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-37 CONFIG_SYNTH_DIV10 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-41 CONFIG_SYNTH_DIV10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.16 CONFIG_SYNTH_DIV12_CC26 Register (Offset = F8h) [Reset = X]

CONFIG_SYNTH_DIV12_CC26 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC26_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC26_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-38 CONFIG_SYNTH_DIV12_CC26 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-42 CONFIG_SYNTH_DIV12_CC26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.17 CONFIG_SYNTH_DIV12_CC13 Register (Offset = FCh) [Reset = X]

CONFIG_SYNTH_DIV12_CC13 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC13_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV12_CC13_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-39 CONFIG_SYNTH_DIV12_CC13 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-43 CONFIG_SYNTH_DIV12_CC13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.18 CONFIG_SYNTH_DIV15 Register (Offset = 100h) [Reset = X]

CONFIG_SYNTH_DIV15 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV15_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV15_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-40 CONFIG_SYNTH_DIV15 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-44 CONFIG_SYNTH_DIV15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.19 CONFIG_SYNTH_DIV30 Register (Offset = 104h) [Reset = X]

CONFIG_SYNTH_DIV30 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV30_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_SYNTH_DIV30_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-41 CONFIG_SYNTH_DIV30 Register

31	30	29	28	27	26	25	24
MIN_ALLOWED_RTRIM				RFC_MDM_DEMIQMC0
R-X				R-X

23	22	21	20	19	18	17	16
RFC_MDM_DEMIQMC0
R-X

15	14	13	12	11	10	9	8
RFC_MDM_DEMIQMC0				LDOVCO_TRIM_OUTPUT
R-X				R-X

7	6	5	4	3	2	1	0
LDOVCO_TRIM_OUTPUT		RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	RESERVED
R-X		R-X	R-0h

Table 12-45 CONFIG_SYNTH_DIV30 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	MIN_ALLOWED_RTRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-12	RFC_MDM_DEMIQMC0	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-6	LDOVCO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
5	RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	RESERVED	R	0h	Reserved

12.4.1.20 FLASH_NUMBER Register (Offset = 164h) [Reset = X]

FLASH_NUMBER is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_NUMBER_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_NUMBER_TABLE.

Return to the Summary Table.

Flash information

Figure 12-42 FLASH_NUMBER Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LOT_NUMBER
R-X

Table 12-46 FLASH_NUMBER Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	LOT_NUMBER	R	X	Number of the manufacturing lot that produced this unit. Default value holds log information from production test.

12.4.1.21 FLASH_COORDINATE Register (Offset = 16Ch) [Reset = X]

FLASH_COORDINATE is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_COORDINATE_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_COORDINATE_TABLE.

Return to the Summary Table.

Flash information

Figure 12-43 FLASH_COORDINATE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
XCOORDINATE																YCOORDINATE
R-X																R-X

Table 12-47 FLASH_COORDINATE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	XCOORDINATE	R	X	X coordinate of this unit on the wafer. Default value holds log information from production test.
15-0	YCOORDINATE	R	X	Y coordinate of this unit on the wafer. Default value holds log information from production test.

12.4.1.22 FLASH_E_P Register (Offset = 170h) [Reset = 4C644C64h]

FLASH_E_P is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_E_P_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_E_P_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-44 FLASH_E_P Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSU								ESU								PVSU								EVSU
R-4Ch								R-64h								R-4Ch								R-64h

Table 12-48 FLASH_E_P Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	PSU	R	4Ch	Internal. Only to be used through TI provided API.
23-16	ESU	R	64h	Internal. Only to be used through TI provided API.
15-8	PVSU	R	4Ch	Internal. Only to be used through TI provided API.
7-0	EVSU	R	64h	Internal. Only to be used through TI provided API.

12.4.1.23 FLASH_C_E_P_R Register (Offset = 174h) [Reset = 0A0A2000h]

FLASH_C_E_P_R is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_C_E_P_R_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_C_E_P_R_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-45 FLASH_C_E_P_R Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RVSU								PV_ACCESS
R-Ah								R-Ah

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
A_EXEZ_SETUP				CVSU
R-2h				R-0h

Table 12-49 FLASH_C_E_P_R Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RVSU	R	Ah	Internal. Only to be used through TI provided API.
23-16	PV_ACCESS	R	Ah	Internal. Only to be used through TI provided API.
15-12	A_EXEZ_SETUP	R	2h	Internal. Only to be used through TI provided API.
11-0	CVSU	R	0h	Internal. Only to be used through TI provided API.

12.4.1.24 FLASH_P_R_PV Register (Offset = 178h) [Reset = 02C10200h]

FLASH_P_R_PV is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_P_R_PV_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_P_R_PV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-46 FLASH_P_R_PV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PH								RH								PVH								PVH2
R-2h								R-C1h								R-2h								R-0h

Table 12-50 FLASH_P_R_PV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	PH	R	2h	Internal. Only to be used through TI provided API.
23-16	RH	R	C1h	Internal. Only to be used through TI provided API.
15-8	PVH	R	2h	Internal. Only to be used through TI provided API.
7-0	PVH2	R	0h	Internal. Only to be used through TI provided API.

12.4.1.25 FLASH_EH_SEQ Register (Offset = 17Ch) [Reset = 0200F000h]

FLASH_EH_SEQ is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_EH_SEQ_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_EH_SEQ_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-47 FLASH_EH_SEQ Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EH								SEQ
R-2h								R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSTAT				SM_FREQUENCY
R-Fh				R-0h

Table 12-51 FLASH_EH_SEQ Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	EH	R	2h	Internal. Only to be used through TI provided API.
23-16	SEQ	R	0h	Internal. Only to be used through TI provided API.
15-12	VSTAT	R	Fh	Internal. Only to be used through TI provided API.
11-0	SM_FREQUENCY	R	0h	Internal. Only to be used through TI provided API.

12.4.1.26 FLASH_VHV_E Register (Offset = 180h) [Reset = 00000001h]

FLASH_VHV_E is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_E_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_E_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-48 FLASH_VHV_E Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VHV_E_START																VHV_E_STEP_HIGHT
R-0h																R-1h

Table 12-52 FLASH_VHV_E Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	VHV_E_START	R	0h	Internal. Only to be used through TI provided API.
15-0	VHV_E_STEP_HIGHT	R	1h	Internal. Only to be used through TI provided API.

12.4.1.27 FLASH_PP Register (Offset = 184h) [Reset = X]

FLASH_PP is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PP_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-49 FLASH_PP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUMP_SU								TRIM3P4								MAX_PP
R-0h								R-X								R-14h

Table 12-53 FLASH_PP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	PUMP_SU	R	0h	Internal. Only to be used through TI provided API.
23-16	TRIM3P4	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-0	MAX_PP	R	14h	Internal. Only to be used through TI provided API.

12.4.1.28 FLASH_PROG_EP Register (Offset = 188h) [Reset = 0FA00010h]

FLASH_PROG_EP is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PROG_EP_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_PROG_EP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-50 FLASH_PROG_EP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MAX_EP																PROGRAM_PW
R-FA0h																R-10h

Table 12-54 FLASH_PROG_EP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MAX_EP	R	FA0h	Internal. Only to be used through TI provided API.
15-0	PROGRAM_PW	R	10h	Internal. Only to be used through TI provided API.

12.4.1.29 FLASH_ERA_PW Register (Offset = 18Ch) [Reset = 00000FA0h]

FLASH_ERA_PW is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_ERA_PW_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_ERA_PW_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-51 FLASH_ERA_PW Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_PW
R-FA0h

Table 12-55 FLASH_ERA_PW Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ERASE_PW	R	FA0h	Internal. Only to be used through TI provided API.

12.4.1.30 FLASH_VHV Register (Offset = 190h) [Reset = X]

FLASH_VHV is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-52 FLASH_VHV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TRIM13_P				RESERVED				VHV_P
R-0h				R-X				R-0h				R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				TRIM13_E				RESERVED				VHV_E
R-0h				R-X				R-0h				R-4h

Table 12-56 FLASH_VHV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-24	TRIM13_P	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-20	RESERVED	R	0h	Reserved
19-16	VHV_P	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-12	RESERVED	R	0h	Reserved
11-8	TRIM13_E	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
7-4	RESERVED	R	0h	Reserved
3-0	VHV_E	R	4h	Internal. Only to be used through TI provided API.

12.4.1.31 FLASH_VHV_PV Register (Offset = 194h) [Reset = X]

FLASH_VHV_PV is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_PV_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_VHV_PV_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-53 FLASH_VHV_PV Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TRIM13_PV				RESERVED				VHV_PV
R-0h				R-X				R-0h				R-8h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VCG2P5								VINH
R-X								R-1h

Table 12-57 FLASH_VHV_PV Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R	0h	Reserved
27-24	TRIM13_PV	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-20	RESERVED	R	0h	Reserved
19-16	VHV_PV	R	8h	Internal. Only to be used through TI provided API.
15-8	VCG2P5	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
7-0	VINH	R	1h	Internal. Only to be used through TI provided API.

12.4.1.32 FLASH_V Register (Offset = 198h) [Reset = X]

FLASH_V is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_V_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_V_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-54 FLASH_V Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSL_P								VWL_P								V_READ								TRIM0P8
R-X								R-X								R-X								R-X

Table 12-58 FLASH_V Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	VSL_P	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-16	VWL_P	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-8	V_READ	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
7-0	TRIM0P8	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.33 USER_ID Register (Offset = 294h) [Reset = X]

USER_ID is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_USER_ID_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_USER_ID_TABLE.

Return to the Summary Table.

User Identification.
Reading this register and the FCFG1:ICEPICK_DEVICE_ID register is the only supported way of identifying a device.
The value of this register will be written to AON_PMCTL:JTAGUSERCODE by boot FW while in safezone.

Figure 12-55 USER_ID Register

31	30	29	28	27	26	25	24
PG_REV				VER		PA	RESERVED
R-1h				R-X		R-X	R-0h

23	22	21	20	19	18	17	16
CC13	SEQUENCE				PKG
R-X	R-X				R-X

15	14	13	12	11	10	9	8
PROTOCOL				RESERVED
R-X				R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 12-59 USER_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	PG_REV	R	1h	Field used to distinguish revisions of the device
27-26	VER	R	X	Version number. 0x0: Bits [25:12] of this register has the stated meaning. Any other setting indicate a different encoding of these bits. Default value differs depending on partnumber.
25	PA	R	X	0: Does not support 20dBm PA 1: Supports 20dBM PA Default value differs depending on partnumber.
24	RESERVED	R	0h	Reserved
23	CC13	R	X	0: CC26xx device type 1: CC13xx device type Default value differs depending on partnumber.
22-19	SEQUENCE	R	X	Sequence. Used to differentiate between marketing/orderable product where other fields of this register are the same (temp range, flash size, voltage range etc) Default value differs depending on partnumber.
18-16	PKG	R	X	Package type. 0x0: 4x4mm QFN (RHB) package 0x1: 5x5mm QFN (RSM) package 0x2: 7x7mm QFN (RGZ) package 0x3: Wafer sale package (naked die) 0x4: WCSP (YFV) 0x5: 7x7mm QFN package with Wettable Flanks Other values are reserved for future use. Packages available for a specific device are shown in the device datasheet. Default value differs depending on partnumber.
15-12	PROTOCOL	R	X	Protocols supported. 0x1: BLE 0x2: RF4CE 0x4: Zigbee/6lowpan 0x8: Proprietary More than one protocol can be supported on same device - values above are then combined. Default value differs depending on partnumber.
11-0	RESERVED	R	0h	Reserved

12.4.1.34 FLASH_OTP_DATA3 Register (Offset = 2B0h) [Reset = X]

FLASH_OTP_DATA3 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA3_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-56 FLASH_OTP_DATA3 Register

31	30	29	28	27	26	25	24
EC_STEP_SIZE
R-0h

23	22	21	20	19	18	17	16
EC_STEP_SIZE	DO_PRECOND	MAX_EC_LEVEL				TRIM_1P7
R-0h	R-0h	R-4h				R-1h

15	14	13	12	11	10	9	8
FLASH_SIZE
R-X

7	6	5	4	3	2	1	0
WAIT_SYSCODE
R-3h

Table 12-60 FLASH_OTP_DATA3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	EC_STEP_SIZE	R	0h	Internal. Only to be used through TI provided API.
22	DO_PRECOND	R	0h	Internal. Only to be used through TI provided API.
21-18	MAX_EC_LEVEL	R	4h	Internal. Only to be used through TI provided API.
17-16	TRIM_1P7	R	1h	Internal. Only to be used through TI provided API.
15-8	FLASH_SIZE	R	X	Internal. Only to be used through TI provided API. Default value differs depending on partnumber.
7-0	WAIT_SYSCODE	R	3h	Internal. Only to be used through TI provided API.

12.4.1.35 ANA2_TRIM Register (Offset = 2B4h) [Reset = X]

ANA2_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANA2_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANA2_TRIM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-57 ANA2_TRIM Register

31	30	29	28	27	26	25	24
RCOSCHFCTRIMFRACT_EN	RCOSCHFCTRIMFRACT					RESERVED	SET_RCOSC_HF_FINE_RESISTOR
R-1h	R-X					R-0h	R-X

23	22	21	20	19	18	17	16
SET_RCOSC_HF_FINE_RESISTOR	ATESTLF_UDIGLDO_IBIAS_TRIM	NANOAMP_RES_TRIM
R-X	R-1h	R-X

15	14	13	12	11	10	9	8
NANOAMP_RES_TRIM	RESERVED			DITHER_EN	DCDC_IPEAK
R-X	R-0h			R-1h	R-0h

7	6	5	4	3	2	1	0
DEAD_TIME_TRIM		DCDC_LOW_EN_SEL			DCDC_HIGH_EN_SEL
R-1h		R-7h			R-7h

Table 12-61 ANA2_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RCOSCHFCTRIMFRACT_EN	R	1h	Internal. Only to be used through TI provided API.
30-26	RCOSCHFCTRIMFRACT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
25	RESERVED	R	0h	Reserved
24-23	SET_RCOSC_HF_FINE_RESISTOR	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
22	ATESTLF_UDIGLDO_IBIAS_TRIM	R	1h	Internal. Only to be used through TI provided API.
21-15	NANOAMP_RES_TRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
14-12	RESERVED	R	0h	Reserved
11	DITHER_EN	R	1h	Internal. Only to be used through TI provided API.
10-8	DCDC_IPEAK	R	0h	Internal. Only to be used through TI provided API.
7-6	DEAD_TIME_TRIM	R	1h	Internal. Only to be used through TI provided API.
5-3	DCDC_LOW_EN_SEL	R	7h	Internal. Only to be used through TI provided API.
2-0	DCDC_HIGH_EN_SEL	R	7h	Internal. Only to be used through TI provided API.

12.4.1.36 LDO_TRIM Register (Offset = 2B8h) [Reset = X]

LDO_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_LDO_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_LDO_TRIM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-58 LDO_TRIM Register

31	30	29	28	27	26	25	24
RESERVED			VDDR_TRIM_SLEEP
R-0h			R-X

23	22	21	20	19	18	17	16
RESERVED					GLDO_CURSRC
R-0h					R-0h

15	14	13	12	11	10	9	8
RESERVED			ITRIM_DIGLDO_LOAD		ITRIM_UDIGLDO
R-0h			R-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED					VTRIM_DELTA
R-0h					R-3h

Table 12-62 LDO_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h	Reserved
28-24	VDDR_TRIM_SLEEP	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-19	RESERVED	R	0h	Reserved
18-16	GLDO_CURSRC	R	0h	Internal. Only to be used through TI provided API.
15-13	RESERVED	R	0h	Reserved
12-11	ITRIM_DIGLDO_LOAD	R	0h	Internal. Only to be used through TI provided API.
10-8	ITRIM_UDIGLDO	R	0h	Internal. Only to be used through TI provided API.
7-3	RESERVED	R	0h	Reserved
2-0	VTRIM_DELTA	R	3h	Internal. Only to be used through TI provided API.

12.4.1.37 MAC_BLE_0 Register (Offset = 2E8h) [Reset = X]

MAC_BLE_0 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_0_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_0_TABLE.

Return to the Summary Table.

MAC BLE Address 0

Figure 12-59 MAC_BLE_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_0_31
R-X

Table 12-63 MAC_BLE_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_0_31	R	X	The first 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test.

12.4.1.38 MAC_BLE_1 Register (Offset = 2ECh) [Reset = X]

MAC_BLE_1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_BLE_1_TABLE.

Return to the Summary Table.

MAC BLE Address 1

Figure 12-60 MAC_BLE_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_32_63
R-X

Table 12-64 MAC_BLE_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_32_63	R	X	The last 32-bits of the 64-bit MAC BLE address Default value holds trim value from production test.

12.4.1.39 MAC_15_4_0 Register (Offset = 2F0h) [Reset = X]

MAC_15_4_0 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_0_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_0_TABLE.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 0

Figure 12-61 MAC_15_4_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_0_31
R-X

Table 12-65 MAC_15_4_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_0_31	R	X	The first 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test.

12.4.1.40 MAC_15_4_1 Register (Offset = 2F4h) [Reset = X]

MAC_15_4_1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MAC_15_4_1_TABLE.

Return to the Summary Table.

MAC IEEE 802.15.4 Address 1

Figure 12-62 MAC_15_4_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_32_63
R-X

Table 12-66 MAC_15_4_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDR_32_63	R	X	The last 32-bits of the 64-bit MAC 15.4 address Default value holds trim value from production test.

12.4.1.41 FLASH_OTP_DATA4 Register (Offset = 308h) [Reset = 98989F9Fh]

FLASH_OTP_DATA4 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA4_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FLASH_OTP_DATA4_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-63 FLASH_OTP_DATA4 Register

31	30	29	28	27	26	25	24
STANDBY_MODE_SEL_INT_WRT	STANDBY_PW_SEL_INT_WRT		DIS_STANDBY_INT_WRT	RESERVED	VIN_AT_X_INT_WRT
R-1h	R-0h		R-1h	R-0h	R-0h

23	22	21	20	19	18	17	16
STANDBY_MODE_SEL_EXT_WRT	STANDBY_PW_SEL_EXT_WRT		DIS_STANDBY_EXT_WRT	RESERVED	VIN_AT_X_EXT_WRT
R-1h	R-0h		R-1h	R-0h	R-0h

15	14	13	12	11	10	9	8
STANDBY_MODE_SEL_INT_RD	STANDBY_PW_SEL_INT_RD		DIS_STANDBY_INT_RD	RESERVED	VIN_AT_X_INT_RD
R-1h	R-0h		R-1h	R-0h	R-7h

7	6	5	4	3	2	1	0
STANDBY_MODE_SEL_EXT_RD	STANDBY_PW_SEL_EXT_RD		DIS_STANDBY_EXT_RD	RESERVED	VIN_AT_X_EXT_RD
R-1h	R-0h		R-1h	R-0h	R-7h

Table 12-67 FLASH_OTP_DATA4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	STANDBY_MODE_SEL_INT_WRT	R	1h	Internal. Only to be used through TI provided API.
30-29	STANDBY_PW_SEL_INT_WRT	R	0h	Internal. Only to be used through TI provided API.
28	DIS_STANDBY_INT_WRT	R	1h	Internal. Only to be used through TI provided API.
27	RESERVED	R	0h	Reserved
26-24	VIN_AT_X_INT_WRT	R	0h	Internal. Only to be used through TI provided API.
23	STANDBY_MODE_SEL_EXT_WRT	R	1h	Internal. Only to be used through TI provided API.
22-21	STANDBY_PW_SEL_EXT_WRT	R	0h	Internal. Only to be used through TI provided API.
20	DIS_STANDBY_EXT_WRT	R	1h	Internal. Only to be used through TI provided API.
19	RESERVED	R	0h	Reserved
18-16	VIN_AT_X_EXT_WRT	R	0h	Internal. Only to be used through TI provided API.
15	STANDBY_MODE_SEL_INT_RD	R	1h	Internal. Only to be used through TI provided API.
14-13	STANDBY_PW_SEL_INT_RD	R	0h	Internal. Only to be used through TI provided API.
12	DIS_STANDBY_INT_RD	R	1h	Internal. Only to be used through TI provided API.
11	RESERVED	R	0h	Reserved
10-8	VIN_AT_X_INT_RD	R	7h	Internal. Only to be used through TI provided API.
7	STANDBY_MODE_SEL_EXT_RD	R	1h	Internal. Only to be used through TI provided API.
6-5	STANDBY_PW_SEL_EXT_RD	R	0h	Internal. Only to be used through TI provided API.
4	DIS_STANDBY_EXT_RD	R	1h	Internal. Only to be used through TI provided API.
3	RESERVED	R	0h	Reserved
2-0	VIN_AT_X_EXT_RD	R	7h	Internal. Only to be used through TI provided API.

12.4.1.42 MISC_TRIM Register (Offset = 30Ch) [Reset = X]

MISC_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_TRIM_TABLE.

Return to the Summary Table.

Miscellaneous Trim Parameters

Figure 12-64 MISC_TRIM Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							TRIM_RECHARGE_COMP_OFFSET
R-0h							R-X

15	14	13	12	11	10	9	8
TRIM_RECHARGE_COMP_OFFSET				TRIM_RECHARGE_COMP_REFLEVEL
R-X				R-X

7	6	5	4	3	2	1	0
TEMPVSLOPE
R-3Bh

Table 12-68 MISC_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16-12	TRIM_RECHARGE_COMP_OFFSET	R	X	Internal. Only to be used through TI provided API.
11-8	TRIM_RECHARGE_COMP_REFLEVEL	R	X	Internal. Only to be used through TI provided API.
7-0	TEMPVSLOPE	R	3Bh	Signed byte value representing the TEMP slope with battery voltage, in degrees C / V, with four fractional bits.

12.4.1.43 RCOSC_HF_TEMPCOMP Register (Offset = 310h) [Reset = 00000003h]

RCOSC_HF_TEMPCOMP is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_RCOSC_HF_TEMPCOMP_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_RCOSC_HF_TEMPCOMP_TABLE.

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Internal. Only to be used through TI provided API.

Figure 12-65 RCOSC_HF_TEMPCOMP Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FINE_RESISTOR								CTRIM
R-0h								R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTRIMFRACT_QUAD								CTRIMFRACT_SLOPE
R-0h								R-3h

Table 12-69 RCOSC_HF_TEMPCOMP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	FINE_RESISTOR	R	0h	Internal. Only to be used through TI provided API.
23-16	CTRIM	R	0h	Internal. Only to be used through TI provided API.
15-8	CTRIMFRACT_QUAD	R	0h	Internal. Only to be used through TI provided API.
7-0	CTRIMFRACT_SLOPE	R	3h	Internal. Only to be used through TI provided API.

12.4.1.44 ICEPICK_DEVICE_ID Register (Offset = 318h) [Reset = 0BB7702Fh]

ICEPICK_DEVICE_ID is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ICEPICK_DEVICE_ID_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ICEPICK_DEVICE_ID_TABLE.

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IcePick Device Identification
Reading this register and the FCFG1:USER_ID register is the only supported way of identifying a device.

Figure 12-66 ICEPICK_DEVICE_ID Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PG_REV				WAFER_ID
R-1h				R-BB77h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WAFER_ID				MANUFACTURER_ID
R-BB77h				R-2Fh

Table 12-70 ICEPICK_DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	PG_REV	R	1h	Field used to distinguish revisions of the device.
27-12	WAFER_ID	R	BB77h	Field used to identify silicon die.
11-0	MANUFACTURER_ID	R	2Fh	Manufacturer code. 0x02F: Texas Instruments

12.4.1.45 FCFG1_REVISION Register (Offset = 31Ch) [Reset = 00000029h]

FCFG1_REVISION is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FCFG1_REVISION_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FCFG1_REVISION_TABLE.

Return to the Summary Table.

Factory Configuration (FCFG1) Revision

Figure 12-67 FCFG1_REVISION Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-29h

Table 12-71 FCFG1_REVISION Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	REV	R	29h	The revision number of the FCFG1 layout. This value will be read by application SW in order to determine which FCFG1 parameters that have valid values. This revision number must be incremented by 1 before any devices are to be produced if the FCFG1 layout has changed since the previous production of devices. Value migth change without warning.

12.4.1.46 MISC_OTP_DATA Register (Offset = 320h) [Reset = X]

MISC_OTP_DATA is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA_TABLE.

Return to the Summary Table.

Misc OTP Data

Figure 12-68 MISC_OTP_DATA Register

31	30	29	28	27	26	25	24
RCOSC_HF_ITUNE				RCOSC_HF_CRIM
R-X				R-X

23	22	21	20	19	18	17	16
RCOSC_HF_CRIM				PER_M
R-X				R-1h

15	14	13	12	11	10	9	8
PER_M	PER_E			RESERVED
R-1h	R-4h			R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 12-72 MISC_OTP_DATA Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RCOSC_HF_ITUNE	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
27-20	RCOSC_HF_CRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
19-15	PER_M	R	1h	Internal. Only to be used through TI provided API.
14-12	PER_E	R	4h	Internal. Only to be used through TI provided API.
11-0	RESERVED	R	0h	Reserved

12.4.1.47 IOCONF Register (Offset = 344h) [Reset = X]

IOCONF is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_IOCONF_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_IOCONF_TABLE.

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IO Configuration

Figure 12-69 IOCONF Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									GPIO_CNT
R-0h									R-X

Table 12-73 IOCONF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-7	RESERVED	R	0h	Reserved
6-0	GPIO_CNT	R	X	Number of available DIOs. Default value differs depending on partnumber.

12.4.1.48 CONFIG_IF_ADC Register (Offset = 34Ch) [Reset = X]

CONFIG_IF_ADC is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_IF_ADC_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_IF_ADC_TABLE.

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Internal. Only to be used through TI provided API.

Figure 12-70 CONFIG_IF_ADC Register

31	30	29	28	27	26	25	24
FF2ADJ				FF3ADJ
R-3h				R-4h

23	22	21	20	19	18	17	16
INT3ADJ				FF1ADJ
R-6h				R-0h

15	14	13	12	11	10	9	8
AAFCAP		INT2ADJ				IFDIGLDO_TRIM_OUTPUT
R-3h		R-Dh				R-X

7	6	5	4	3	2	1	0
IFDIGLDO_TRIM_OUTPUT			IFANALDO_TRIM_OUTPUT
R-X			R-X

Table 12-74 CONFIG_IF_ADC Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	FF2ADJ	R	3h	Internal. Only to be used through TI provided API.
27-24	FF3ADJ	R	4h	Internal. Only to be used through TI provided API.
23-20	INT3ADJ	R	6h	Internal. Only to be used through TI provided API.
19-16	FF1ADJ	R	0h	Internal. Only to be used through TI provided API.
15-14	AAFCAP	R	3h	Internal. Only to be used through TI provided API.
13-10	INT2ADJ	R	Dh	Internal. Only to be used through TI provided API.
9-5	IFDIGLDO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
4-0	IFANALDO_TRIM_OUTPUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.49 CONFIG_OSC_TOP Register (Offset = 350h) [Reset = X]

CONFIG_OSC_TOP is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_OSC_TOP_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_CONFIG_OSC_TOP_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-71 CONFIG_OSC_TOP Register

31	30	29	28	27	26	25	24
RESERVED		XOSC_HF_ROW_Q12				XOSC_HF_COLUMN_Q12
R-0h		R-7h				R-1FFh

23	22	21	20	19	18	17	16
XOSC_HF_COLUMN_Q12
R-1FFh

15	14	13	12	11	10	9	8
XOSC_HF_COLUMN_Q12						RCOSCLF_CTUNE_TRIM
R-1FFh						R-X

7	6	5	4	3	2	1	0
RCOSCLF_CTUNE_TRIM						RCOSCLF_RTUNE_TRIM
R-X						R-0h

Table 12-75 CONFIG_OSC_TOP Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29-26	XOSC_HF_ROW_Q12	R	7h	Internal. Only to be used through TI provided API.
25-10	XOSC_HF_COLUMN_Q12	R	1FFh	Internal. Only to be used through TI provided API.
9-2	RCOSCLF_CTUNE_TRIM	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
1-0	RCOSCLF_RTUNE_TRIM	R	0h	Internal. Only to be used through TI provided API.

12.4.1.50 SOC_ADC_ABS_GAIN Register (Offset = 35Ch) [Reset = X]

SOC_ADC_ABS_GAIN is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_ABS_GAIN_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_ABS_GAIN_TABLE.

Return to the Summary Table.

AUX_ADC Gain in Absolute Reference Mode

Figure 12-72 SOC_ADC_ABS_GAIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_ADC_ABS_GAIN_TEMP1
R-X

Table 12-76 SOC_ADC_ABS_GAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	SOC_ADC_ABS_GAIN_TEMP1	R	X	SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated in production test.. Default value holds log information from production test.

12.4.1.51 SOC_ADC_REL_GAIN Register (Offset = 360h) [Reset = X]

SOC_ADC_REL_GAIN is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REL_GAIN_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REL_GAIN_TABLE.

Return to the Summary Table.

AUX_ADC Gain in Relative Reference Mode

Figure 12-73 SOC_ADC_REL_GAIN Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_ADC_REL_GAIN_TEMP1
R-X

Table 12-77 SOC_ADC_REL_GAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	SOC_ADC_REL_GAIN_TEMP1	R	X	SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated in production test.. Default value holds trim value from production test.

12.4.1.52 SOC_ADC_OFFSET_INT Register (Offset = 368h) [Reset = X]

SOC_ADC_OFFSET_INT is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_OFFSET_INT_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_OFFSET_INT_TABLE.

Return to the Summary Table.

AUX_ADC Temperature Offsets in Absolute Reference Mode

Figure 12-74 SOC_ADC_OFFSET_INT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED								SOC_ADC_REL_OFFSET_TEMP1
R-0h								R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								SOC_ADC_ABS_OFFSET_TEMP1
R-0h								R-X

Table 12-78 SOC_ADC_OFFSET_INT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-16	SOC_ADC_REL_OFFSET_TEMP1	R	X	SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. Default value holds trim value from production test.
15-8	RESERVED	R	0h	Reserved
7-0	SOC_ADC_ABS_OFFSET_TEMP1	R	X	SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed 8-bit number. Calculated in production test.. Default value holds trim value from production test.

12.4.1.53 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register (Offset = 36Ch) [Reset = X]

SOC_ADC_REF_TRIM_AND_OFFSET_EXT is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-75 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		SOC_ADC_REF_VOLTAGE_TRIM_TEMP1
R-0h		R-X

Table 12-79 SOC_ADC_REF_TRIM_AND_OFFSET_EXT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	0h	Reserved
5-0	SOC_ADC_REF_VOLTAGE_TRIM_TEMP1	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.54 AMPCOMP_TH1 Register (Offset = 370h) [Reset = FF7B828Eh]

AMPCOMP_TH1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-76 AMPCOMP_TH1 Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
HPMRAMP3_LTH						RESERVED
R-1Eh						R-0h

15	14	13	12	11	10	9	8
HPMRAMP3_HTH						IBIASCAP_LPTOHP_OL_CNT
R-20h						R-Ah

7	6	5	4	3	2	1	0
IBIASCAP_LPTOHP_OL_CNT		HPMRAMP1_TH
R-Ah		R-Eh

Table 12-80 AMPCOMP_TH1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	0h	Reserved
23-18	HPMRAMP3_LTH	R	1Eh	Internal. Only to be used through TI provided API.
17-16	RESERVED	R	0h	Reserved
15-10	HPMRAMP3_HTH	R	20h	Internal. Only to be used through TI provided API.
9-6	IBIASCAP_LPTOHP_OL_CNT	R	Ah	Internal. Only to be used through TI provided API.
5-0	HPMRAMP1_TH	R	Eh	Internal. Only to be used through TI provided API.

12.4.1.55 AMPCOMP_TH2 Register (Offset = 374h) [Reset = 6B8B0303h]

AMPCOMP_TH2 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH2_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_TH2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-77 AMPCOMP_TH2 Register

31	30	29	28	27	26	25	24
LPMUPDATE_LTH						RESERVED
R-1Ah						R-0h

23	22	21	20	19	18	17	16
LPMUPDATE_HTM						RESERVED
R-22h						R-0h

15	14	13	12	11	10	9	8
ADC_COMP_AMPTH_LPM						RESERVED
R-0h						R-0h

7	6	5	4	3	2	1	0
ADC_COMP_AMPTH_HPM						RESERVED
R-0h						R-0h

Table 12-81 AMPCOMP_TH2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	LPMUPDATE_LTH	R	1Ah	Internal. Only to be used through TI provided API.
25-24	RESERVED	R	0h	Reserved
23-18	LPMUPDATE_HTM	R	22h	Internal. Only to be used through TI provided API.
17-16	RESERVED	R	0h	Reserved
15-10	ADC_COMP_AMPTH_LPM	R	0h	Internal. Only to be used through TI provided API.
9-8	RESERVED	R	0h	Reserved
7-2	ADC_COMP_AMPTH_HPM	R	0h	Internal. Only to be used through TI provided API.
1-0	RESERVED	R	0h	Reserved

12.4.1.56 AMPCOMP_CTRL1 Register (Offset = 378h) [Reset = FF483F47h]

AMPCOMP_CTRL1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_CTRL1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_AMPCOMP_CTRL1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-78 AMPCOMP_CTRL1 Register

31	30	29	28	27	26	25	24
RESERVED	AMPCOMP_REQ_MODE	RESERVED
R-0h	R-1h	R-0h

23	22	21	20	19	18	17	16
IBIAS_OFFSET				IBIAS_INIT
R-4h				R-8h

15	14	13	12	11	10	9	8
LPM_IBIAS_WAIT_CNT_FINAL
R-3Fh

7	6	5	4	3	2	1	0
CAP_STEP				IBIASCAP_HPTOLP_OL_CNT
R-4h				R-7h

Table 12-82 AMPCOMP_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	AMPCOMP_REQ_MODE	R	1h	Internal. Only to be used through TI provided API.
29-24	RESERVED	R	0h	Reserved
23-20	IBIAS_OFFSET	R	4h	Internal. Only to be used through TI provided API.
19-16	IBIAS_INIT	R	8h	Internal. Only to be used through TI provided API.
15-8	LPM_IBIAS_WAIT_CNT_FINAL	R	3Fh	Internal. Only to be used through TI provided API.
7-4	CAP_STEP	R	4h	Internal. Only to be used through TI provided API.
3-0	IBIASCAP_HPTOLP_OL_CNT	R	7h	Internal. Only to be used through TI provided API.

12.4.1.57 ANABYPASS_VALUE2 Register (Offset = 37Ch) [Reset = FFFFC3FFh]

ANABYPASS_VALUE2 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANABYPASS_VALUE2_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_ANABYPASS_VALUE2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-79 ANABYPASS_VALUE2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		XOSC_HF_IBIASTHERM
R-0h		R-3FFh

Table 12-83 ANABYPASS_VALUE2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-14	RESERVED	R	0h	Reserved
13-0	XOSC_HF_IBIASTHERM	R	3FFh	Internal. Only to be used through TI provided API.

12.4.1.58 VOLT_TRIM Register (Offset = 388h) [Reset = X]

VOLT_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_VOLT_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_VOLT_TRIM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-80 VOLT_TRIM Register

31	30	29	28	27	26	25	24
RESERVED			VDDR_TRIM_HH
R-0h			R-X

23	22	21	20	19	18	17	16
RESERVED			VDDR_TRIM_H
R-0h			R-X

15	14	13	12	11	10	9	8
RESERVED			VDDR_TRIM_SLEEP_H
R-0h			R-X

7	6	5	4	3	2	1	0
RESERVED			TRIMBOD_H
R-0h			R-X

Table 12-84 VOLT_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h	Reserved
28-24	VDDR_TRIM_HH	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
23-21	RESERVED	R	0h	Reserved
20-16	VDDR_TRIM_H	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-13	RESERVED	R	0h	Reserved
12-8	VDDR_TRIM_SLEEP_H	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
7-5	RESERVED	R	0h	Reserved
4-0	TRIMBOD_H	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.59 OSC_CONF Register (Offset = 38Ch) [Reset = X]

OSC_CONF is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_OSC_CONF_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_OSC_CONF_TABLE.

Return to the Summary Table.

OSC Configuration

Figure 12-81 OSC_CONF Register

31	30	29	28	27	26	25	24
RESERVED		ADC_SH_VBUF_EN	ADC_SH_MODE_EN	ATESTLF_RCOSCLF_IBIAS_TRIM	XOSCLF_REGULATOR_TRIM		XOSCLF_CMIRRWR_RATIO
R-0h		R-1h	R-1h	R-0h	R-0h		R-0h

23	22	21	20	19	18	17	16
XOSCLF_CMIRRWR_RATIO			XOSC_HF_FAST_START		XOSC_OPTION	RESERVED
R-0h			R-1h		R-X	R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED
R-X

Table 12-85 OSC_CONF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29	ADC_SH_VBUF_EN	R	1h	Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN.
28	ADC_SH_MODE_EN	R	1h	Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN.
27	ATESTLF_RCOSCLF_IBIAS_TRIM	R	0h	Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM.
26-25	XOSCLF_REGULATOR_TRIM	R	0h	Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM.
24-21	XOSCLF_CMIRRWR_RATIO	R	0h	Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO.
20-19	XOSC_HF_FAST_START	R	1h	Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START.
18	XOSC_OPTION	R	X	0: XOSC_HF unavailable (may not be bonded out) 1: XOSC_HF available (default) Default value differs depending on partnumber.
17-0	RESERVED	R	X	Reserved

12.4.1.60 FREQ_OFFSET Register (Offset = 390h) [Reset = X]

FREQ_OFFSET is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FREQ_OFFSET_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_FREQ_OFFSET_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-82 FREQ_OFFSET Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED
R-X

Table 12-86 FREQ_OFFSET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	RESERVED	R	X	Reserved

12.4.1.61 MISC_OTP_DATA_1 Register (Offset = 398h) [Reset = E08403F8h]

MISC_OTP_DATA_1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA_1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_MISC_OTP_DATA_1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-83 MISC_OTP_DATA_1 Register

31	30	29	28	27	26	25	24
RESERVED			PEAK_DET_ITRIM		HP_BUF_ITRIM
R-0h			R-0h		R-0h

23	22	21	20	19	18	17	16
LP_BUF_ITRIM		DBLR_LOOP_FILTER_RESET_VOLTAGE		HPM_IBIAS_WAIT_CNT
R-2h		R-0h		R-100h

15	14	13	12	11	10	9	8
HPM_IBIAS_WAIT_CNT						LPM_IBIAS_WAIT_CNT
R-100h						R-3Fh

7	6	5	4	3	2	1	0
LPM_IBIAS_WAIT_CNT				IDAC_STEP
R-3Fh				R-8h

Table 12-87 MISC_OTP_DATA_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	0h	Reserved
28-27	PEAK_DET_ITRIM	R	0h	Internal. Only to be used through TI provided API.
26-24	HP_BUF_ITRIM	R	0h	Internal. Only to be used through TI provided API.
23-22	LP_BUF_ITRIM	R	2h	Internal. Only to be used through TI provided API.
21-20	DBLR_LOOP_FILTER_RESET_VOLTAGE	R	0h	Internal. Only to be used through TI provided API.
19-10	HPM_IBIAS_WAIT_CNT	R	100h	Internal. Only to be used through TI provided API.
9-4	LPM_IBIAS_WAIT_CNT	R	3Fh	Internal. Only to be used through TI provided API.
3-0	IDAC_STEP	R	8h	Internal. Only to be used through TI provided API.

12.4.1.62 SHDW_DIE_ID_0 Register (Offset = 3D0h) [Reset = X]

SHDW_DIE_ID_0 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_0_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_0_TABLE.

Return to the Summary Table.

Shadow of DIE_ID_0 register in eFuse

Figure 12-84 SHDW_DIE_ID_0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID_31_0
R-X

Table 12-88 SHDW_DIE_ID_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID_31_0	R	X	Shadow of DIE_ID_0 register in eFuse row number 5 Default value depends on eFuse value.

12.4.1.63 SHDW_DIE_ID_1 Register (Offset = 3D4h) [Reset = X]

SHDW_DIE_ID_1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_1_TABLE.

Return to the Summary Table.

Shadow of DIE_ID_1 register in eFuse

Figure 12-85 SHDW_DIE_ID_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID_63_32
R-X

Table 12-89 SHDW_DIE_ID_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID_63_32	R	X	Shadow of DIE_ID_1 register in eFuse row number 6 Default value depends on eFuse value.

12.4.1.64 SHDW_DIE_ID_2 Register (Offset = 3D8h) [Reset = X]

SHDW_DIE_ID_2 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_2_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_2_TABLE.

Return to the Summary Table.

Shadow of DIE_ID_2 register in eFuse

Figure 12-86 SHDW_DIE_ID_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID_95_64
R-X

Table 12-90 SHDW_DIE_ID_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID_95_64	R	X	Shadow of DIE_ID_2 register in eFuse row number 7 Default value depends on eFuse value.

12.4.1.65 SHDW_DIE_ID_3 Register (Offset = 3DCh) [Reset = X]

SHDW_DIE_ID_3 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_3_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_DIE_ID_3_TABLE.

Return to the Summary Table.

Shadow of DIE_ID_3 register in eFuse

Figure 12-87 SHDW_DIE_ID_3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID_127_96
R-X

Table 12-91 SHDW_DIE_ID_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ID_127_96	R	X	Shadow of DIE_ID_3 register in eFuse row number 8 Default value depends on eFuse value.

12.4.1.66 SHDW_OSC_BIAS_LDO_TRIM Register (Offset = 3F8h) [Reset = X]

SHDW_OSC_BIAS_LDO_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_OSC_BIAS_LDO_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_OSC_BIAS_LDO_TRIM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-88 SHDW_OSC_BIAS_LDO_TRIM Register

31	30	29	28	27	26	25	24
RESERVED					TRIMMAG
R-0h					R-X

23	22	21	20	19	18	17	16
TRIMMAG	TRIMIREF					ITRIM_DIG_LDO
R-X	R-X					R-X

15	14	13	12	11	10	9	8
VTRIM_DIG				VTRIM_COARSE
R-X				R-X

7	6	5	4	3	2	1	0
RCOSCHF_CTRIM
R-X

Table 12-92 SHDW_OSC_BIAS_LDO_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-23	TRIMMAG	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
22-18	TRIMIREF	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
17-16	ITRIM_DIG_LDO	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
15-12	VTRIM_DIG	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
11-8	VTRIM_COARSE	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
7-0	RCOSCHF_CTRIM	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.

12.4.1.67 SHDW_ANA_TRIM Register (Offset = 3FCh) [Reset = X]

SHDW_ANA_TRIM is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_ANA_TRIM_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_SHDW_ANA_TRIM_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-89 SHDW_ANA_TRIM Register

31	30	29	28	27	26	25	24
RESERVED	ALT_VDDR_TRIM	DET_LOGIC_DIS	BOD_BANDGAP_TRIM_CNF_EXT		BOD_BANDGAP_TRIM_CNF		VDDR_ENABLE_PG1
R-0h	R-X	R-X	R-X		R-X		R-X

23	22	21	20	19	18	17	16
VDDR_OK_HYS	IPTAT_TRIM		VDDR_TRIM
R-X	R-X		R-X

15	14	13	12	11	10	9	8
TRIMBOD_INTMODE					TRIMBOD_EXTMODE
R-X					R-X

7	6	5	4	3	2	1	0
TRIMBOD_EXTMODE		TRIMTEMP
R-X		R-X

Table 12-93 SHDW_ANA_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30	ALT_VDDR_TRIM	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
29	DET_LOGIC_DIS	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
28-27	BOD_BANDGAP_TRIM_CNF_EXT	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
26-25	BOD_BANDGAP_TRIM_CNF	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
24	VDDR_ENABLE_PG1	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
23	VDDR_OK_HYS	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
22-21	IPTAT_TRIM	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
20-16	VDDR_TRIM	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
15-11	TRIMBOD_INTMODE	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
10-6	TRIMBOD_EXTMODE	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.
5-0	TRIMTEMP	R	X	Internal. Only to be used through TI provided API. Default value depends on eFuse value.

12.4.1.68 DAC_BIAS_CNF Register (Offset = 40Ch) [Reset = X]

DAC_BIAS_CNF is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_BIAS_CNF_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_BIAS_CNF_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-90 DAC_BIAS_CNF Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED						LPM_TRIM_IOUT
R-0h						R-X

15	14	13	12	11	10	9	8
LPM_TRIM_IOUT				LPM_BIAS_WIDTH_TRIM			LPM_BIAS_BACKUP_EN
R-X				R-0h			R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 12-94 DAC_BIAS_CNF Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	0h	Reserved
17-12	LPM_TRIM_IOUT	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
11-9	LPM_BIAS_WIDTH_TRIM	R	0h	Internal. Only to be used through TI provided API.
8	LPM_BIAS_BACKUP_EN	R	0h	Internal. Only to be used through TI provided API.
7-0	RESERVED	R	0h	Reserved

12.4.1.69 TFW_PROBE Register (Offset = 418h) [Reset = X]

TFW_PROBE is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_PROBE_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_PROBE_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-91 TFW_PROBE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

Table 12-95 TFW_PROBE Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	REV	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.70 TFW_FT Register (Offset = 41Ch) [Reset = X]

TFW_FT is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_FT_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_TFW_FT_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-92 TFW_FT Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

Table 12-96 TFW_FT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	REV	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.71 DAC_CAL0 Register (Offset = 420h) [Reset = X]

DAC_CAL0 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL0_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL0_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-93 DAC_CAL0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SOC_DAC_VOUT_CAL_DECOUPLE_C2
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_DAC_VOUT_CAL_DECOUPLE_C1
R-X

Table 12-97 DAC_CAL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SOC_DAC_VOUT_CAL_DECOUPLE_C2	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-0	SOC_DAC_VOUT_CAL_DECOUPLE_C1	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.72 DAC_CAL1 Register (Offset = 424h) [Reset = X]

DAC_CAL1 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL1_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL1_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-94 DAC_CAL1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SOC_DAC_VOUT_CAL_PRECH_C2
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_DAC_VOUT_CAL_PRECH_C1
R-X

Table 12-98 DAC_CAL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SOC_DAC_VOUT_CAL_PRECH_C2	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-0	SOC_DAC_VOUT_CAL_PRECH_C1	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.73 DAC_CAL2 Register (Offset = 428h) [Reset = X]

DAC_CAL2 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL2_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL2_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-95 DAC_CAL2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SOC_DAC_VOUT_CAL_ADCREF_C2
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_DAC_VOUT_CAL_ADCREF_C1
R-X

Table 12-99 DAC_CAL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SOC_DAC_VOUT_CAL_ADCREF_C2	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-0	SOC_DAC_VOUT_CAL_ADCREF_C1	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

12.4.1.74 DAC_CAL3 Register (Offset = 42Ch) [Reset = X]

DAC_CAL3 is shown in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL3_FIGURE and described in #FCFG1_FCFG1_MMAP1_FCFG1_ALL_DAC_CAL3_TABLE.

Return to the Summary Table.

Internal. Only to be used through TI provided API.

Figure 12-96 DAC_CAL3 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SOC_DAC_VOUT_CAL_VDDS_C2
R-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SOC_DAC_VOUT_CAL_VDDS_C1
R-X

Table 12-100 DAC_CAL3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	SOC_DAC_VOUT_CAL_VDDS_C2	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.
15-0	SOC_DAC_VOUT_CAL_VDDS_C1	R	X	Internal. Only to be used through TI provided API. Default value holds trim value from production test.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REV
R-X