SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The two system-level interrupts RF_CPE0 and RF_CPE1 can be produced from a number of low-level interrupts produced by the CPE. Each of these low-level interrupts can be mapped to RF_CPE0 or RF_CPE1 using the RFCPEISL register. In addition, interrupt generation at system level may be switched on and off using the RFCPEIEN register.
In case of an event that triggers a low-level interrupt, the corresponding bit in the RFCPEIFG register is set to 1. Whenever a bit in RFCPEIFG and the corresponding bit in RFCPEIEN are both 1, the system-level interrupt selected in RFCPEISL is raised. This means that the interrupt service routine (ISR) must clear the bits in RFCPEIFG that correspond to low-level interrupts that have been processed.
The register description for RFCPEIFG in Section 26.11.2 provides a list of the available interrupts.
Clear bits in RFCPEIFG by writing 0 to those bits, while any bits written to 1 remain unchanged.
When clearing bits in the RFCPEIFG register, interrupts may be lost if a read-modify-write operation is done because interrupt flags that became active between the read and write operation might be lost. Thus, clearing an interrupt flag should be done as follows:
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~(1 << irq_no);and not as:
HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) &= ~(1 << irq_no); // wrong