SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The µDMA Channel 7 is dedicated to transfer ADC samples from the ADC FIFO. Use the sequence that follows to set up a µDMA transfer:
The AUX_ADC_IRQ event sets when the µDMA completes data block transfer. AUX_ADC_IRQ is mapped to System CPU interrupt line 32 (for further description, see EVENT:CPUIRQSEL32 in Section 6.7.2).
This event will also set when the ADC FIFO either overflows or underflows, as indicated by AUX_ANAIF:ADCFIFOSTAT.