SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The connections required to use the SSI port are the following four pins:
The device communicating with the bootloader drives the FSS pins (SSI0_RX, SSI0_CLK, and SSI0), while the CC13x2x7 and CC26x2x7 device platform drives the SSI0_TX pin.
The format used for SSI communications is the Motorola format with SPH set to 1 and SPO set to 1 (see Figure 23-9 for more information on this format). The SSI interface has a hardware requirement that limits the maximum rate of the SSI clock to be at most 1/12 the frequency of the SSI module clock
(48 MHz / 12 = 4 MHz).
The master must take special consideration (regarding the use of the SSI0 interface) due to the functionality of not configuring any output pins before the external master device has selected a serial interface.
On the first packet transferred by the master, no data is received from the bootloader while the bootloader clocks out the bits in the first byte of the packet.
When the bootloader detects that 1 byte has been received on SSI0_RX, the bootloader configures the SSI0_TX output pin.
Before transmitting the next byte in the first packet, the master must include a small delay to ensure that the bootloader has completed the configuration of the SSI0_TX output pin.