SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
8.5.2.1 Clock Gating
As seen in Figure 8-6, the peripheral modules have conditional clock gates that depend on the system CPU mode. The clock of a module may be enabled or disabled when the system CPU mode changes.
Example:
- PRCM:I2CCLKGR.CLK_EN = 1
- PRCM:I2CCLKGS.CLK_EN = 0
- PRCM:I2CCLKGDS.CLK_EN = 1
These settings result in the I2C clock running when the system CPU is in run mode and deep sleep mode, while the I2C clock is disabled, and when system CPU is in sleep mode.
When set in deep sleep mode, the system CPU remains in sleep mode for a few clock cycles during the transition. An application that requires a continuous module clock enables all clock-gate registers for the module during the transition while the system CPU changes modes.
Clock control can be controlled independently of system CPU mode by use of the modules clock control for all modes, AM_CLK_EN.
Example:
PRCM:I2CCLKGR.AM_CLK_EN = 1
This setting results in the I2C clock running independently of system CPU mode.
Clocks in MCU_VD are hardware controlled during power cycling, so it is not required to control the module clocks when power domains are powered up or down.
Figure 8-6 Clocks in MCU_VD