SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
13.6.1 Introduction
The processing steps of the AES module are the basis for the performance calculations. The following three major steps are identified for crypto operations using DMA:
- Initialization (setup and initialization of the engines, DMA, and so forth)
- Data processing for the complete message
- Finalization (reading out the result, status checking)
The orange sections (full processing) of Figure 13-2 correspond to Step 1 and Step 3. Step 1 and Step 3 are under control of the host CPU, and therefore are dependent on the performance of the host. Step 2 corresponds to the green section (data processing) in Figure 13-2 and is fully handled by the hardware, which is not dependent on the performance of the host CPU.
The full processing part is required once per processing command, and precedes the processing of the first data block. The data processing blocks depend on the amount of data to be processed by the command. The finalization is required when the operation produces a result digest or TAG.
The number of required blocks is determined by the block size requirements of the algorithms selected by the command. The AES block size is 128 bits.
The Hash block size is 512 bits for SHA-256 and SHA-224, and the block size is 1024 bits for SHA-512 and SHA-384.
For longer data streams, the data processing time approaches the theoretical maximum throughput. For operations that use the slave interface as alternative for the DMA, the performance depends on the performance of the host CPU.
Figure 13-2 Symmetric Crypto Processing Steps