SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The FLASH memory is organized as a set of 8 kB blocks that can be individually erased. An individual 64-bit word can be programmed to change bits from 1 to 0. Erasing a block causes the entire contents of the block to be reset to all 1s. The 8 kB blocks are paired with sets of 8 kB blocks that can be individually protected by being marked as read-only. Read-only blocks cannot be erased or programmed, which protects the contents of those blocks from being modified. The read-only lock bits are located in CCFG. As such a mass erase or erasing the last flash page (with CCFG) will disable the read-only lock.
There is a restriction on how many write operations are allowed to a FLASH row between erases. A row is comprised of 2048 bits (or 256 bytes). The FLASH memory is divided evenly into physical rows. One may perform a maximum of 83 write operations within a row between erases. If more than 83 write operations are performed before re-erasure, one may see unwritten bits in the row that are erased (in a logic 1 state) become programmed (change to a logic 0 state). User software must take care of this restriction, there is no hardware that checks and informs if this restriction is violated.
The FLASH block is mainly clocked by the 48 MHz system clock.