SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
This chapter describes the cJTAG and JTAG interface for on-chip debug support.
| ID | Description |
|---|---|
| [JTAG 1] | IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a 1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics Engineers, Inc. |
| [JTAG 2] | IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture |