SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The RAM block operates as follows:
The current mode is shown in the VIMS:STAT.MODE register, and mode switching is controlled through the VIMS:CTL.MODE register. Figure 9-2 shows the mode transitions. All mode changes are software initiated. The invalidating state is a transition state controlled by hardware. Invalidation initializes the entire content of the RAM block and takes 1029 clock periods to perform.
Once a mode change is initiated, shown in the VIMS:STATUS.MODE_CHANGING register, the mode change must complete before another mode change can be initiated. The VIMS:CTL.MODE register is blocked for updates during a mode change.