SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The VIMS provides arbitration between the CPU and the system bus. The arbitration is configurable between round-robin and static, through the VIMS:CTL.ARB_CFG register. The static arbitration is enabled by default and gives the CPU priority over the system bus.
The system arbiter allows accesses to occur simultaneously, provided that the CPU and the system bus have different target memories. If, for example, a CPU access causes a cache hit, a system bus access can access the FLASH simultaneously.