The CPU uses the TPIU macro inside the processor to support the serial wire viewer (SWV) interface (a single-line interface). Use the following sequence to enable SWV output on the CPU:
- Enable the trace system by setting
CPU_SCS:DEMCR.TRCENA (see Section 3.9.4).
- Unlock ITM configuration by writing to the Lock
Access Register CPU_ITM:LAR (see Section 3.9.3).
- Enable ITM by setting CPU_ITM:TCR.ITMENA (see
Section 3.9.3
).
- Enable the desired stimulus port (0 to 31) in
CPU_ITM:TER (see Section 3.9.3).
- Change formatter configuration if needed
CPU_TPIU:FFCR (see Section 3.9.5
).
- Change the pin protocol if needed CPU_TPIU:SPPR
(see Section 3.9.5).
- Set the baud rate in CPU_TPIU:ACPR (see Section 3.9.5).
- The SWV can be mapped to DIOn by writing the
corresponding port ID in the IOC:IOCFGn (see Section 14.10.3). For more details, see Section 14.
Writes to the CPU_ITM:STIMn registers (assuming that they are enabled) trigger a transmit on SWV output if the FIFO is not full.