SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The sequencer program ROM has up to 2048 bits (24 bits each) synchronous Read-Only memory with the interface described in Table 13-45 (direction from the PKA engine; data bus direction naming from the sequencer program ROM).
| Signal | Direction | Function |
|---|---|---|
| rom_me | OUT | Active-high memory enable; maximum output delay is 50% of the clock cycle. |
| rom_addr[10:0] | OUT | Address output bus; maximum output delay time is 50% of the clock cycle. |
| rom_rdata[23:0] | IN | Data input bus; must be valid before 70% of the clock cycle. |