SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. Internal FIFO memories buffer the transmit and receive paths, allowing independent storage of up to eight 16-bit values in both transmit and receive modes. The SSI also supports the μDMA interface. The TX and RX FIFOs can be programmed as destination or source addresses in the μDMA module. The μDMA operation is enabled by setting the appropriate bits in the SSI:DMACR register.