SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
22.4.1 Transmit and Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the TX FIFO. The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits (LSB first), parity bit, and the stop bits, according to the programmed configuration in the control registers. For details, see Figure 22-2.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse is detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data written to the RX FIFO.
Figure 22-2 UART Character Frame