SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5
Table 2-2 lists the memory-mapped registers for the BPU registers. All register offset addresses not listed in Table 2-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | BP_CTRL | Breakpoint Control Register | Go |
8h | BP_COMP0 | Breakpoint Comparator Register 0 | Go |
Ch | BP_COMP1 | Breakpoint Comparator Register 1 | Go |
10h | BP_COMP2 | Breakpoint Comparator Register 2 | Go |
14h | BP_COMP3 | Breakpoint Comparator Register 3 | Go |
FD0h | PIDR4 | Peripheral ID Register 4 | Go |
FD4h | PIDR5 | Peripheral ID Register 5 | Go |
FD8h | PIDR6 | Peripheral ID Register 6 | Go |
FDCh | PIDR7 | Peripheral ID Register 7 | Go |
FE0h | PIDR0 | Peripheral ID Register 0 | Go |
FE4h | PIDR1 | Peripheral ID Register 1 | Go |
FE8h | PIDR2 | Peripheral ID Register 2 | Go |
FECh | PIDR3 | Peripheral ID Register 3 | Go |
FF0h | CIDR0 | Component ID Register 0 | Go |
FF4h | CIDR1 | Component ID Register 1 | Go |
FF8h | CIDR2 | Component ID Register 2 | Go |
FFCh | CIDR3 | Component ID Register 3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
BP_CTRL is shown in Table 2-4.
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Breakpoint Control Register
Use the Breakpoint Control Register to enable the Breakpoint block
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | NUM_CODE | R | 4h | Number of comparators. |
3-2 | RESERVED | R | 0h | Reserved |
1 | KEY | W | 0h | Key field. To write to the Breakpoint Control Register, you must write a 1 to this write-only bit. This bit reads as zero. |
0 | ENABLE | R/W | 0h | Breakpoint unit enable bit. DBGRESETn clears the ENABLE bit. 0h = Breakpoint unit disabled 1h = Breakpoint unit enabled |
BP_COMP0 is shown in Table 2-5.
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Breakpoint Comparator Register 0
Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | BP_MATCH | R/W | 0h | This selects what happens when the COMP address is matched 0h = no breakpoint generated 1h = set breakpoint on lower halfword, upper is unaffected 2h = set breakpoint on upper halfword, lower is unaffected 3h = set breakpoint on both lower and upper halfwords |
29 | RESERVED | R | 0h | Reserved |
28-2 | COMP | R/W | 0h | Comparison address, UNKNOWN on reset. |
1 | RESERVED | R | 0h | Reserved |
0 | ENABLE | R/W | 0h | Compare enable for Breakpoint Comparator Register 0. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit. 0h = Breakpoint Comparator Register 0 compare disabled 1h = Breakpoint Comparator Register 0 compare enabled |
BP_COMP1 is shown in Table 2-6.
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Breakpoint Comparator Register 1
Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | BP_MATCH | R/W | 0h | This selects what happens when the COMP address is matched 0h = No breakpoint generated 1h = Set breakpoint on lower halfword, upper is unaffected 2h = Set breakpoint on upper halfword, lower is unaffected 3h = Set breakpoint on both lower and upper halfwords |
29 | RESERVED | R | 0h | Reserved |
28-2 | COMP | R/W | 0h | Comparison address. Although it is architecturally Unpredictable whether breakpoint matches on the address of the second halfword of a 32-bit instruction to generates a debug event, in this processor it is predictable and a debug event is generated. |
1 | RESERVED | R | 0h | Reserved |
0 | ENABLE | R/W | 0h | Comparison address, UNKNOWN on reset. 0h = Breakpoint Comparator Register 1 compare disabled 1h = Breakpoint Comparator Register 1 compare enabled |
BP_COMP2 is shown in Table 2-7.
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Breakpoint Comparator Register 2
Use the Breakpoint Comparator Registers to store the values to compare with the PC address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | BP_MATCH | R/W | 0h | This selects what happens when the COMP address is matched 0h = No breakpoint matching 1h = Set breakpoint on lower halfword, upper is unaffected 2h = Set breakpoint on upper halfword, lower is unaffected 3h = Set breakpoint on both lower and upper halfwords |
29 | RESERVED | R | 0h | Reserved |
28-2 | COMP | R/W | 0h | Comparison address, UNKNOWN on reset. |
1 | RESERVED | R | 0h | Reserved |
0 | ENABLE | R/W | 0h | Compare enable for Breakpoint Comparator Register 2. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit. 0h = Breakpoint Comparator Register 2 compare disabled 1h = Breakpoint Comparator Register 2 compare enabled |
BP_COMP3 is shown in Table 2-8.
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Breakpoint Comparator Register 3
Use the Breakpoint Comparator Registers to store the values to compare with the instruction address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | BP_MATCH | R/W | 0h | This selects what happens when the COMP address is matched 0h = No breakpoint generated 1h = Set breakpoint on lower halfword, upper is unaffected 2h = Set breakpoint on upper halfword, lower is unaffected 3h = Set breakpoint on both lower and upper halfwords |
29 | RESERVED | R | 0h | Reserved |
28-2 | COMP | R/W | 0h | Comparison address, UNKNOWN on reset. |
1 | RESERVED | R | 0h | Reserved |
0 | ENABLE | R/W | 0h | Compare enable for Breakpoint Comparator Register 3. The ENABLE bit of BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE bit. 0h = Breakpoint Comparator Register 3 compare disabled 1h = Breakpoint Comparator Register 3 compare enabled |
PIDR4 is shown in Table 2-9.
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Peripheral ID Register 4
Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | SIZE | R | 0h | This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. |
3-0 | DES_2 | R | 4h | Number of JEDEC continuation codes. Indicates the designer of the component (along with the identity code) |
PIDR5 is shown in Table 2-10.
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Peripheral ID Register 5
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR6 is shown in Table 2-11.
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Peripheral ID Register 6
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR7 is shown in Table 2-12.
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Peripheral ID Register 7
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR0 is shown in Table 2-13.
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Peripheral ID Register 0
Part of the set of Peripheral Identification registers. Contains part of the designer specific part number.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PART_0 | R | Bh | Bits [7:0] of the component's part number. This is selected by the designer of the component. |
PIDR1 is shown in Table 2-14.
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Peripheral ID Register 1
Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | DES_0 | R | Bh | Bits [3:0] of the JEDEC identity code indicating the designer of the component (along with the continuation code) |
3-0 | PART_1 | R | 0h | Bits [11:8] of the component's part number. This is selected by the designer of the component. |
PIDR2 is shown in Table 2-15.
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Peripheral ID Register 2
Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | REVISION | R | 0h | The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. |
3 | JEDEC | R | 1h | Always set. Indicates that a JEDEC assigned value is used |
2-0 | DES_1 | R | 3h | Bits [6:4] of the JEDEC identity code indicating the designer of the component (along with the continuation code) |
PIDR3 is shown in Table 2-16.
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Peripheral ID Register 3
Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | REVAND | R | 0h | This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. |
3-0 | CMOD | R | 0h | Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. |
CIDR0 is shown in Table 2-17.
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Component ID Register 0
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_0 | R | Dh | Contains bits [7:0] of the component identification |
CIDR1 is shown in Table 2-18.
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Component ID Register 1
A component identification register, that indicates that the identification registers are present. This register also indicates the component class.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | CLASS | R | Eh | Class of the component. for example, . ROM table, CoreSight component and so on. Constitutes bits [15:12] of the component identification. |
3-0 | PRMBL_1 | R | 0h | Contains bits [11:8] of the component identification |
CIDR2 is shown in Table 2-19.
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Component ID Register 2
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_2 | R | 5h | Contains bits [23:16] of the component identification |
CIDR3 is shown in Table 2-20.
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Component ID Register 3
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_3 | R | B1h | Contains bits [31:24] of the component identification |