SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5
Consider AES encryption has to be performed on 4 blocks of 128-bit plaintext which is stored in SRAM. The primary control structure of µDMA Channel 4 which is assigned to AES channel A, can be configured as below, to transfer the plaintext from SRAM to AES.
Transfer size | 16 words |
Source end pointer | Plaintext memory location in SRAM |
Destination end pointer | [DMA.DMACHA] |
Source Increment | 32 bits |
Destination Increment | None |
Arbitration size | 4 words |
Transfer Mode | Basic |
µDMA channel 5 which is assigned to AES channel B, can be configured as below, to transfer ciphertext from AES to SRAM
Transfer size | 16 words |
Source end pointer | [DMA.DMACHB] |
Destination end pointer | SRAM memory location to store ciphertext |
Source Increment | None |
Destination Increment | 32 bits |
Arbitration size | 4 words |
Transfer Mode | Basic |
Refer to Chapter 15 for more details on configuring µDMA channels.