SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
To stop a DMA transfer and abort the operation, the host disables a channel using the CRYPTO:DMACHnCTL registers. When the EN bit of this register is set to 0, no new DMA transfer is requested by this channel and the current active transfer is finished. Alternatively, all active channels can be stopped by activating the DMAC soft reset with the CRYPTO:DMASWRESET register.
When stopping the DMAC, the host must stop all active channels.
The state of the DMAC channel must be checked using the CRYPTO:DMASTAT register. When the CHx_ACT bit of this register for the disabled channel is set to 0, the DMAC channel stops.
To stop the DMAC in combination with the AES engine, the AES engine must be set in Idle mode first, which is done by writing zeroes to the length registers, followed by disabling all modes in the CRYPTO:AESCTL register.
Stopping the DMAC channels might leave the master control module in an unfinished state, due to pending events from the engines that will never occur. Therefore, to correctly recover the engine, the SWRESET register must issue the master control soft reset after all active DMAC channels are stopped.