SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 20-54 lists the memory-mapped registers for the AUX_AIODIO registers. All register offset addresses not listed in Table 20-54 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | IOMODE | Input Output Mode | Section 20.8.2.1 |
4h | GPIODIE | General Purpose Input Output Digital Input Enable | Section 20.8.2.2 |
8h | IOPOE | Input Output Peripheral Output Enable | Section 20.8.2.3 |
Ch | GPIODOUT | General Purpose Input Output Data Out | Section 20.8.2.4 |
10h | GPIODIN | General Purpose Input Output Data In | Section 20.8.2.5 |
14h | GPIODOUTSET | General Purpose Input Output Data Out Set | Section 20.8.2.6 |
18h | GPIODOUTCLR | General Purpose Input Output Data Out Clear | Section 20.8.2.7 |
1Ch | GPIODOUTTGL | General Purpose Input Output Data Out Toggle | Section 20.8.2.8 |
20h | IO0PSEL | Input Output 0 Peripheral Select | Section 20.8.2.9 |
24h | IO1PSEL | Input Output 1 Peripheral Select | Section 20.8.2.10 |
28h | IO2PSEL | Input Output 2 Peripheral Select | Section 20.8.2.11 |
2Ch | IO3PSEL | Input Output 3 Peripheral Select | Section 20.8.2.12 |
30h | IO4PSEL | Input Output 4 Peripheral Select | Section 20.8.2.13 |
34h | IO5PSEL | Input Output 5 Peripheral Select | Section 20.8.2.14 |
38h | IO6PSEL | Input Output 6 Peripheral Select | Section 20.8.2.15 |
3Ch | IO7PSEL | Input Output 7 Peripheral Select | Section 20.8.2.16 |
40h | IOMODEL | Input Output Mode Low | Section 20.8.2.17 |
44h | IOMODEH | Input Output Mode High | Section 20.8.2.18 |
Complex bit access types are encoded to fit into small table cells. Table 20-55 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
IOMODE is shown in Table 20-56.
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Input Output Mode
This register controls pull-up, pull-down, and output mode for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-14 | IO7 | R/W | 0h | Selects mode for AUXIO[8i+7].
0h = Output Mode: When IOPOE bit 7 is 0: GPIODOUT bit 7 drives AUXIO[8i+7]. When IOPOE bit 7 is 1: The signal selected by IO7PSEL.SRC drives AUXIO[8i+7]. 1h = Input Mode: When GPIODIE bit 7 is 0: AUXIO[8i+7] is enabled for analog signal transfer. When GPIODIE bit 7 is 1: AUXIO[8i+7] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is driven low. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 7 is 0: - If GPIODOUT bit 7 is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 7 is 1: AUXIO[8i+7] is driven high. When IOPOE bit 7 is 1: - If signal selected by IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. |
13-12 | IO6 | R/W | 0h | Selects mode for AUXIO[8i+6].
0h = Output Mode: When IOPOE bit 6 is 0: GPIODOUT bit 6 drives AUXIO[8i+6]. When IOPOE bit 6 is 1: The signal selected by IO6PSEL.SRC drives AUXIO[8i+6]. 1h = Input Mode: When GPIODIE bit 6 is 0: AUXIO[8i+6] is enabled for analog signal transfer. When GPIODIE bit 6 is 1: AUXIO[8i+6] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is driven low. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 6 is 0: - If GPIODOUT bit 6 is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 6 is 1: AUXIO[8i+6] is driven high. When IOPOE bit 6 is 1: - If signal selected by IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. |
11-10 | IO5 | R/W | 0h | Selects mode for AUXIO[8i+5].
0h = Output Mode: When IOPOE bit 5 is 0: GPIODOUT bit 5 drives AUXIO[8i+5]. When IOPOE bit 5 is 1: The signal selected by IO5PSEL.SRC drives AUXIO[8i+5]. 1h = Input Mode: When GPIODIE bit 5 is 0: AUXIO[8i+5] is enabled for analog signal transfer. When GPIODIE bit 5 is 1: AUXIO[8i+5] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is driven low. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 5 is 0: - If GPIODOUT bit 5 is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 5 is 1: AUXIO[8i+5] is driven high. When IOPOE bit 5 is 1: - If signal selected by IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. |
9-8 | IO4 | R/W | 0h | Selects mode for AUXIO[8i+4].
0h = Output Mode: When IOPOE bit 4 is 0: GPIODOUT bit 4 drives AUXIO[8i+4]. When IOPOE bit 4 is 1: The signal selected by IO4PSEL.SRC drives AUXIO[8i+4]. 1h = Input Mode: When GPIODIE bit 4 is 0: AUXIO[8i+4] is enabled for analog signal transfer. When GPIODIE bit 4 is 1: AUXIO[8i+4] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is driven low. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 4 is 0: - If GPIODOUT bit 4 is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 4 is 1: AUXIO[8i+4] is driven high. When IOPOE bit 4 is 1: - If signal selected by IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. |
7-6 | IO3 | R/W | 0h | Selects mode for AUXIO[8i+3].
0h = Output Mode: When IOPOE bit 3 is 0: GPIODOUT bit 3 drives AUXIO[8i+3]. When IOPOE bit 3 is 1: The signal selected by IO3PSEL.SRC drives AUXIO[8i+3]. 1h = Input Mode: When GPIODIE bit 3 is 0: AUXIO[8i+3] is enabled for analog signal transfer. When GPIODIE bit 3 is 1: AUXIO[8i+3] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is driven low. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 3 is 0: - If GPIODOUT bit 3 is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 3 is 1: AUXIO[8i+3] is driven high. When IOPOE bit 3 is 1: - If signal selected by IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. |
5-4 | IO2 | R/W | 0h | Select mode for AUXIO[8i+2].
0h = Output Mode: When IOPOE bit 2 is 0: GPIODOUT bit 2 drives AUXIO[8i+2]. When IOPOE bit 2 is 1: The signal selected by IO2PSEL.SRC drives AUXIO[8i+2]. 1h = Input Mode: When GPIODIE bit 2 is 0: AUXIO[8i+2] is enabled for analog signal transfer. When GPIODIE bit 2 is 1: AUXIO[8i+2] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is driven low. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 2 is 0: - If GPIODOUT bit 2 is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 2 is 1: AUXIO[8i+2] is driven high. When IOPOE bit 2 is 1: - If signal selected by IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. |
3-2 | IO1 | R/W | 0h | Select mode for AUXIO[8i+1].
0h = Output Mode: When IOPOE bit 1 is 0: GPIODOUT bit 1 drives AUXIO[8i+1]. When IOPOE bit 1 is 1: The signal selected by IO1PSEL.SRC drives AUXIO[8i+1]. 1h = Input Mode: When GPIODIE bit 1 is 0: AUXIO[8i+1] is enabled for analog signal transfer. When GPIODIE bit 1 is 1: AUXIO[8i+1] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is driven low. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 1 is 0: - If GPIODOUT bit 1 is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 1 is 1: AUXIO[8i+1] is driven high. When IOPOE bit 1 is 1: - If signal selected by IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. |
1-0 | IO0 | R/W | 0h | Select mode for AUXIO[8i+0].
0h = Output Mode: When IOPOE bit 0 is 0: GPIODOUT bit 0 drives AUXIO[8i+0]. When IOPOE bit 0 is 1: The signal selected by IO0PSEL.SRC drives AUXIO[8i+0]. 1h = Input Mode: When GPIODIE bit 0 is 0: AUXIO[8i+0] is enabled for analog signal transfer. When GPIODIE bit 0 is 1: AUXIO[8i+0] is enabled for digital input. 2h = Open-Drain Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is driven low. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. 3h = Open-Source Mode: When IOPOE bit 0 is 0: - If GPIODOUT bit 0 is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If GPIODOUT bit 0 is 1: AUXIO[8i+0] is driven high. When IOPOE bit 0 is 1: - If signal selected by IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or pulled. This depends on IOC:IOCFGn.PULL_CTL. - If signal selected by IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. |
GPIODIE is shown in Table 20-57.
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General Purpose Input Output Digital Input Enable
This register controls input buffers for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to enable digital input buffer for AUXIO[8i+n]. Write 0 to bit index n in this bit vector to disable digital input buffer for AUXIO[8i+n]. You must enable the digital input buffer for AUXIO[8i+n] to read the pin value in GPIODIN. You must disable the digital input buffer for analog input or pins that float to avoid current leakage. |
IOPOE is shown in Table 20-58.
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Input Output Peripheral Output Enable
This register selects the output source for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from source given in [IOnPSEL.*]. Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be driven from bit n in GPIODOUT. |
GPIODOUT is shown in Table 20-59.
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General Purpose Input Output Data Out
The output data register is used to set data on AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. You must clear bit n in IOPOE to connect bit n in this bit vector to AUXIO[8i+n]. |
GPIODIN is shown in Table 20-60.
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General Purpose Input Output Data In
This register provides synchronized input data for AUXIO that are controlled by instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R | 0h | Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit n is set. Otherwise, bit n is read as 0. |
GPIODOUTSET is shown in Table 20-61.
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General Purpose Input Output Data Out Set
Set bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to set GPIODOUT bit n. Read value is 0. |
GPIODOUTCLR is shown in Table 20-62.
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General Purpose Input Output Data Out Clear
Clear bits in GPIODOUT instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. Read value is 0. |
GPIODOUTTGL is shown in Table 20-63.
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General Purpose Input Output Data Out Toggle
Toggle bits in GPIODOUT in instance i of AUX_AIODIO. Hence, in formulas below i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | IO7_0 | R/W | 0h | Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. Read value is 0. |
IO0PSEL is shown in Table 20-64.
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Input Output 0 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 1.
To avoid glitches on AUXIO[8i+0] you must configure this register while IOPOE bit 0 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO1PSEL is shown in Table 20-65.
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Input Output 1 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 1.
To avoid glitches on AUXIO[8i+1] you must configure this register while IOPOE bit 1 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO2PSEL is shown in Table 20-66.
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Input Output 2 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 1.
To avoid glitches on AUXIO[8i+2] you must configure this register while IOPOE bit 2 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO3PSEL is shown in Table 20-67.
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Input Output 3 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 1.
To avoid glitches on AUXIO[8i+3] you must configure this register while IOPOE bit 3 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO4PSEL is shown in Table 20-68.
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Input Output 4 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 1.
To avoid glitches on AUXIO[8i+4] you must configure this register while IOPOE bit 4 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO5PSEL is shown in Table 20-69.
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Input Output 5 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 1.
To avoid glitches on AUXIO[8i+5] you must configure this register while IOPOE bit 5 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO6PSEL is shown in Table 20-70.
Return to the Summary Table.
Input Output 6 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 1.
To avoid glitches on AUXIO[8i+6] you must configure this register while IOPOE bit 6 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IO7PSEL is shown in Table 20-71.
Return to the Summary Table.
Input Output 7 Peripheral Select
This register selects a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 1.
To avoid glitches on AUXIO[8i+7] you must configure this register while IOPOE bit 7 is 0.
In the formulas i = 0 for AUX_AIODIO0, i = 1 for AUX_AIODIO1, and so forth.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | SRC | R/W | 0h | Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is set.
0h = Peripheral output mux selects event selected by AUX_EVCTL:EVOBSCFG 1h = Peripheral output mux selects AUX_SPIM SCLK. 2h = Peripheral output mux selects AUX_SPIM MOSI. 3h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 4h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 5h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 6h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 7h = Peripheral output mux selects asynchronous version of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. |
IOMODEL is shown in Table 20-72.
Return to the Summary Table.
Input Output Mode Low
This is an alias register for IOMODE.IO0 thru IOMODE.IO3.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-6 | IO3 | R/W | 0h | See IOMODE.IO3. |
5-4 | IO2 | R/W | 0h | See IOMODE.IO2. |
3-2 | IO1 | R/W | 0h | See IOMODE.IO1. |
1-0 | IO0 | R/W | 0h | See IOMODE.IO0. |
IOMODEH is shown in Table 20-73.
Return to the Summary Table.
Input Output Mode High
This is an alias register for IOMODE.IO4 thru IOMODE.IO7.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-6 | IO7 | R/W | 0h | See IOMODE.IO7. |
5-4 | IO6 | R/W | 0h | See IOMODE.IO6. |
3-2 | IO5 | R/W | 0h | See IOMODE.IO5. |
1-0 | IO4 | R/W | 0h | See IOMODE.IO4. |