SWRA574B
October 2017 – February 2020
AWR1243
,
AWR2243
AWR2243 Cascade
Trademarks
1
Cascaded AWR2243 System
2
Synchronization of AWR2243 Chips
2.1
20 GHz (FMCW) RF LO Sync
2.2
Digital Frame Sync
2.2.1
Frame (Burst) and Chirp Timing in AWR2243
2.2.2
Frame (Burst) and Chirp Timing in a Cascaded System
2.2.3
Inter Chip Imbalance of Digital Sync Timing
2.3
40 MHz (System) Reference Clock Synchronization
3
Connectivity
3.1
20 GHz LO Sync Pins Connectivity
3.2
DIG_SYNC Connectivity
3.3
40 MHz (System) Reference Clock Connectivity
4
20 GHz LO Sync Link Budget
5
Software Messaging
5.1
Configuration of Devices
5.2
Configuration of Frames
5.2.1
Similar Configuration Across AWR2243 Devices
5.2.2
Dissimilar Configuration Across AWR2243 Devices
5.3
Triggering of Frames
5.4
Example Usage
5.5
Other Usages
6
Advantages of AWR2243 Cascading System
7
References
Revision History
7
References
AWR2243 Interface Control Document (ICD)
Texas Instruments:
Programming Chirp Parameters in TI Radar Devices
Texas Instruments:
AWR2243 Single-Chip 76- to 81-GHz FMCW Transceiver Data Sheet
MMWCAS-RF-EVM
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