SWRA591 April   2019 CC1310 , CC1350

 

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2.1 Convolutional Encoder

Figure 2 shows the coder implemented in the DSSS modulation scheme. A convolutional encoder is defined by its rate, its constraint-length K (number of stages in the encoding shift register) and the connections between its internal states. The convolutional encoder used in this case has K=4 and only supports ½ rate (that is, for every input bit, the encoder produces two output bits).

The connections between internal states are a fundamental way of defining the code. The implemented encoder is based on non-systematic, non-recursive convolutional code.

figure-02-swra591.gifFigure 2. K=4, Rate = ½, Convolutional Encoder for WB-DSSS Modes

The black dots in Figure 2 represent logic XOR operations. The two output bits (a0, a1) from the encoder are serialized in a way that a0 is transmitted first and a1 is transmitted last.