1 Power Management Framework

Texas Instruments' low power xWRL6432 radar sensors detect objects and motion by emitting and receiving Frequency Modulated Continuous Waves (FMCW). Designed for low-power applications such as video doorbells, security systems, gesture controlled HMI and automotive intruder detection, the xWRL6432 offers multiple low-power modes that allow the radar device to minimize power consumption depending on the use-case needs. This application note details the ways to reduce power consumption through effective system design, chirping profile, and application software. Additionally, this application note will cover techniques for measuring power on the xWRL6432 device.

Power Domains

Figure 1-1 xWRL6432 Device Architecture

Typical Radar Application Flow

Figure 1-2 shows a typical radar application flow. The terminology used in the flow is explained in Table 1-2.

Figure 1-2 Typical Application Flow during 1 frame of operation.

As the graphic above shows, the radar device chirps a number of times on regular intervals, processes all the data collected, then goes into a low-power Interframe Idle state. The next section describes each of the above states in greater detail.

Power State Descriptions

Active

The Active state is when the device is chirping or processing chirp data. In this state, the device can either be in a Data Acquisition substate, which is when data is being collected by transmitting and receiving chirps, or in a Data Processing substate, when the samples recorded in the Data Acquisition substate are being processed together. When the device is in the Data Acquisition sub-state, both the APPSS_PS and the FEC_PD must be on, however, when the device is in the Data Processing substate, the FEC_PD may be powered down to reduce power usage. The Data Acquisition substate within the Active state draws the highest power level of the device.

Idle

The Idle state occurs when the device is not actively chirping or processing data. There are three types of Idle states (Interchirp Idle, Interburst Idle and Interframe Idle). The Interchirp Idle and Interburst Idle states are completely handled by the device firmware. As the device cycles between chirps and bursts, it will go to these states automatically. By comparison, the Interframe Idle state that the device enters between frames may be configured and modified by the user. The time requirements for each idle state are as follows:

The Deep Sleep state is an application-driven option for the xWRL6432 when it is already in the Interframe Idle state. Deep Sleep is the lowest possible power state designed state in the device, where nearly all the device power domains, including the Application sub-system (APPSS), along with Hardware Accelerator (HWA) and Front-End Controller sub-system (FECSS) are powered off to save a significant amount of power. Deep sleep can be triggered by the application when the device enters the Interframe Idle state. Deep Sleep requires a nominal amount of time to deinitialize software and power down hardware, then power up hardware and reinitialize the software after the end of the deep sleep period. Typical times for this are around 2 milliseconds, but they will vary depending on the deep sleep options selected.

Even though the entire device being is almost completely powered down, it does not need to reboot after waking up from deep sleep. The contents of the device, such as the application image and chirp profile are retained across deep sleep cycles in the APPSS/FECSS memories.

A device may exit from the deep sleep state through the Sleep Counter, UART RX, SPI CS, GPIO, and RTC.

Power Domains in the Different Power Modes

The table below shows the states of the different power domains in the different modes. Note that many of these may be modified, and different portions of the power domains may be clock-gated or powered down by the user.