4 Reducing Power in the Interframe Idle and Deep Sleep States

Reducing Power in the Idle State

The Interframe Idle state is a software programmable state in the device. In this mode, the device is either waiting for the command from the external host or transferring the captured samples over the SPI or CAN interface. No radar processing or data acquisition is happening in the device while the oscillator circuitry and perhaps PLL (depending upon the host interface peripheral used) of the device is up and running. In the Interframe Idle state, the user may power down or clock-gate portions of the device, lowering power.

The xWRL6432 allows the following peripherals to be turned off with the sequences shown below.

Clocking

Instead of powering off peripherals completely, users may instead choose to reduce the amount of power they consume by altering the peripherals' clocking options. The most common ways to accomplish this are the following :

• Changing the Input Clock Source

Many peripherals can be fed from multiple different clock sources. Typically, faster clock sources cause peripherals to draw more power during operation. [5] enumerates the clock control (CLKCTL) registers available for changing the input clock to the peripherals.

• Further Clock Reduction via Clock Dividers

After the clock source to a peripheral has been set, it can be divided to reduce its frequency, which subsequently reduces the power it draws. The same clock control (CLKCTL) registers mentioned above, found in [5], allow users to divide the input clocks down to the desired frequency.

• Clock-Gating

Clock-gating keeps the input clock to a peripheral from ticking. This means the peripheral will not operate until it is no-longer clock gated. Clock-gating draws more power than shutting off the peripheral altogether, but it also requires less time and energy to power back on from the off state, making it advantageous for quicker responsiveness. The same clock control (CLKCTL) registers mentioned above, found in [5], allow users to gate the input clocks to the peripherals.

Reducing Power in Deep Sleep Mode

Deep Sleep is the lowest possible hardware power state of the device. In deep sleep, nearly the entire device is powered off to save a considerable amount of power. Just the vital contents on the device, such as the application image and chirp profile are retained in deep sleep. These preserve the device's context, allowing it to re-enter operation without a reboot.

The benefits of Deep Sleep mode are seen most prominently in low duty cycle applications like presence detection, in which the device is only active for short amounts of time. For the remainder of the time, when the device does not need to be active, the system can go into Deep Sleep mode, saving power and extending lifetimes for battery powered applications.

The power consumed in the Deep Sleep state depends mainly on two factors: the amount of memory retained and the states of the IO pins during deep sleep.

Memory Retention on the xWRL6432 in Deep Sleep

The xWRL6432 has 1 MB of memory divided across the APPSS, FECSS and HWASS Power Domains. More power is consumed in deep sleep mode when more memory is retained.

The xWRL6432 device can save power by reducing the amount of memory retained in the Deep Sleep mode. On the xWRL6432, memory instances consume approximately 45 µW / 64kB in power-down retention mode. If memory within a cluster is not retained, it will consume approximately 20 µW/64 kB. To further save power when memory is not retained, some memory clusters on the xWRL6432 are grouped together, and power switches are deployed on the corresponding SRAM power rails. If all the clusters in a group are not retained during Deep Sleep, switches for the group are opened, completely powering off the group, causing the memory to consume 0 µW/kB while completely powered off (no retention).

Figure 4-1 Switchable and Unswitchable Memory.

Powering down specific memory banks can be accomplished using SysConfig, a TI tool used to configure many TI devices. When disabling RAM Retention, ensure that none of the data needed for operation in the subsequent frame, such as device code, is stored in the RAM that is not retained. If this occurs, it will prevent proper operation, as the information the device needs to operate will have been erased.

Impact of Digital IO Power

There are various digital peripheral IOs, for instance, SPI, UART, CAN-FD, I2C, LIN, etc. in the xWRL6432 to transfer data, download images or establish a connection with an external MCU. Since the deep sleep power state draws very little power, any floating node can cause significant current leakage. It is therefore important to approriately park these IOs to their relevant pull up/pull down or high impendance state when the xWRL6432 device is in a deep sleep mode. This can be accomplished again using SysConfig.

To minimize power consumption, TI recommends parking all available pins in deep sleep. Pins needed to serve as wakeup sources for the xWRL6432 can remain in their default input states. Additionally, pins that route signals out of the xWRL6432 that need to maintain their state while the device is in deep sleep (say for example a reset line to another device, or an LED light) can also remain in their default output states.