SWRU612 December 2023 CC3300 , CC3301 , CC3301MOD , CC3351
For optimal power consumption, the slow clock can be generated externally by an oscillator or sourced from elsewhere in the system. The external source must meet the requirements shown in Table 2-4. This clock should be fed into the CC330x pin Slow_CLK_IN and should be stable before nReset is deasserted and device is enabled.
Parameter | Description | MIN | TYP | MAX | Unit | |
---|---|---|---|---|---|---|
Input slow clock frequency | Square wave | 32768 | Hz | |||
Frequency accuracy | Inital + temperature + aging | ±250 | ppm | |||
Input Duty cycle | 30 | 50 | 70 | % | ||
Tr/Tf | Rise and fall time | 10% to 90% (rise) and 90% to 10% (fall) of digital signal level | 100 | ns | ||
VIL | Input low level | 0 | 0.35 x VIO | V | ||
VIH | Input high level | 0.65 x VIO | 1.95 | V | ||
Input impedence | 1 | MΩ | ||||
Input capacitance | 5 | pF |