SWRU622A August 2024 – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP
On a STC_WARM or WARM reset reason, as seen by the RBL flow in Figure 2-1, the appropriate STC tests and image verification is performed and then the execution jumps to the address stored in the boot vector (TOP_PRCM:PC_REGISTER2). This address is typically the start of the user application. In this flow, there is necessary HW infrastructure provisioned to ensure that the memory contents are retained on a warm reset cycle with the power to the device maintained to be intact. The RBL will not by default reload an image from SDF in this flow.
A Warm reset is internally generated by the device, or triggered by device pin WARM_RESET. A write to the TOP_PRCM:RST_SOFT_RESET register generates the reset. The WARM_RESET can be used to reset the device from the external world or to report the reset to the external world if it is generated by an internal source such as watchdog timer.