SWRZ092B April 2021 – March 2022 IWR6843AOP
DMA Read from Unimplemented Address Space may Result in DMA Hang Scenario
IWR6843AOP ES1.0
The MSS DMA generates a BER (Bus Error) interrupt when the DMA detects a bus error due to a read from unimplemented address space. This interrupt is available on VIM Interrupt Channel-70 for DMA1 and VIM Interrupt Channel-51 for DMA2 .This read from unimplemented address space results in a hang condition in the DMA infrastructure bridge that connects it to the main interconnect.
Implication: A DMA read from an unimplemented address can result in a DMA hang condition. In the resulting state the DMA will not respond to any further DMA requests.
The MSS CR4F processor will have to invoke a warm reset or generate an nERROR, if it receives a DMA BER error.