SWRZ092B April 2021 – March 2022 IWR6843AOP
Occasional Failures Observed During Calibration of the Radar Subsystem
IWR6843AOP ES1.0 and IWR6843AOP ES2.0
Rare occurrences of failures have been observed in the Dual-Clock Comparator (DCC) module, as a result the APLL or Synthesizer may report a failure.
Workaround #1:
Any APLL calibration failure needs to be responded with a reset cycle.
or
Workaround #2:
Any SYNTH calibration failure reported by the BSS will require an RFinit.