SWRZ092B April   2021  – March 2022 IWR6843AOP

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#10
    3.     MSS#11
    4.     MSS#12
    5.     MSS#13
    6.     MSS#14
    7.     MSS#16
    8.     MSS#17
    9.     MSS#18
    10.     MSS#19
    11.     MSS#20
    12.     MSS#21
    13.     MSS#22
    14.     MSS#23
    15.     MSS#24
    16.     MSS#25
    17.     MSS#26
    18.     MSS#27
    19.     MSS#28
    20.     MSS#29
    21.     MSS#30
    22.     MSS#31
    23.     MSS#32
    24.     MSS#33
    25.     MSS#34
    26.     MSS#35
    27.     MSS#36
    28.     MSS#37B
    29.     MSS#38A
    30.     MSS#39
    31.     MSS#40
    32.     MSS#41
    33.     MSS#42A
    34.     MSS#43A
    35.     MSS#44A
    36.     MSS#45
    37. 6.1 MSS#50
    38. 6.2 MSS#51
    39.     ANA#11B
    40.     ANA#12A
    41.     ANA#13B
    42.     ANA#14
    43.     ANA#16
    44.     ANA#17A
    45.     ANA#18B
    46.     ANA#19
    47.     ANA#20
    48.     ANA#22A
    49. 6.3 ANA#27A
    50.     ANA#30
    51.     ANA#31
    52.     DSS#01
    53.     DSS#02
    54.     DSS#03
    55.     DSS#05
    56.     DSS#07
    57.     PACKAGE#01
    58.     PACKAGE#02
  7. 7Trademarks
  8. 8Revision History

MSS#41

Issuing WARM_RESET can Cause Bootloader Failure Which Results in Failure to Load the Application From Serial Flash

Revision(s) Affected:

IWR6843AOP ES1.0 and IWR6843AOP ES2.0

Description:

WARM_RESET issued by application software (via register write), internal watchdog trigger, or external pin invocation can cause bootloader failure. This results in failure to load the application from serial flash

  1. Occurrence of WARM_RESET resets all configuration registers to default pre boot ROM values.
  2. Change in register values can affect settings of APLL clock, resulting in the PLL clock leaking into digital subsystems of device. This can create an invalid state of a specific clock divider in the PLL clock domain which is subsequently not initialized by the WARM_RESET functionality.
  3. Once this clock divider state is reached the subsequent bootloader execution hangs while trying to read the QSPI serial flash for program load (the QSPI is dependent upon the clock divider). This necessitates a power-cycle or nRESET for a successful recovery.

Workaround(s):

Avoid WARM_RESET. Use an external nRESET to initiate device reset with either an external watchdog or PMIC initiated reset sequence.