SWRZ092B April 2021 – March 2022 IWR6843AOP
DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet
IWR6843AOP ES1.0 and IWR6843AOP ES2.0
The BUSY flag in the DMMGLBCTRL register should be set when the DMM starts receiving a packet or has data in its internal buffers. However, the BUSY flag (DMMGLBCTRL.24) may not get set when the DMM starts receiving a packet under the following condition:
Wait for a number of DMMCLK cycles (for example, 95 DMMCLK cycles) beyond the longest reception and deserialization time needed for a given packet size and DMM port configuration, before checking the status of the BUSY flag, and after the DMM ON/OFF bit field (DMMGLBCTRL.[3:0]) has been programmed to OFF.