SWRZ099B April   2020  – March 2022 AWR6843AOP

 

  1. 1Introduction
  2. 2Device Nomenclature
  3. 3Device Markings
  4. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  5. 5Advisory to Silicon Variant / Revision Map
  6. 6Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#26
    3.     MSS#27
    4.     MSS#28
    5.     MSS#29
    6.     MSS#30
    7.     MSS#31
    8.     MSS#32
    9.     MSS#33
    10.     MSS#34
    11.     MSS#36
    12.     MSS#37B
    13.     MSS#38A
    14.     MSS#39
    15.     MSS#40
    16.     MSS#41
    17.     MSS#42A
    18.     MSS#43A
    19.     MSS#44A
    20.     MSS#45
    21. 6.1 MSS#50
    22. 6.2 MSS#51
    23.     ANA#11B
    24.     ANA#12A
    25.     ANA#13B
    26.     ANA#14
    27.     ANA#16
    28.     ANA#17A
    29.     ANA#18B
    30.     ANA#19
    31.     ANA#20
    32.     ANA#22A
    33.     ANA#27A
    34.     ANA#30
    35.     ANA#31
    36.     PACKAGE#02
  7. 7Trademarks
  8. 8Revision History

MSS#38A

GPIO Glitch During Power-Up

Revision(s) Affected:

AWR6843AOP ES2.0

Description:

During the 3.3-V supply ramp, the GPIO outputs could possibly see a short glitch (rising above the 0 V for a short duration), if the 3.3V supply powers up before the 1.8V supply. This GPIO glitch cannot be avoided by just a pulldown resistor. If the GPIO glitch during boot-up is high enough, it could be falsely detected as a “high”.

Workaround(s):

Powering up the 1.8V supply before the 3.3V supply resolved the issue. Incase that is not feasible, AND the GPIO is used for critical controls where glitch cannot be tolerated, the GPIO output should be gated by the nRESET signal of the xWR device.

Using a tri-state buffer (for example: SN74LVC1G126-Q1) externally to isolate the GPIO output from the system until the nRESET of xWR device is released. At this point, all the supplies are expected to be stable.