SWRZ102C November   2021  – December 2024 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#46
    9. 5.2  MSS#48
    10. 5.3  MSS#49
    11. 5.4  MSS#52
    12. 5.5  MSS#53
    13. 5.6  MSS#54
    14. 5.7  MSS#55
    15. 5.8  MSS#56
    16. 5.9  MSS#57
    17. 5.10 MSS#58
    18. 5.11 MSS#59
    19. 5.12 MSS#60
    20. 5.13 MSS#61
    21. 5.14 MSS#62
    22.     MSS#66
    23. 5.15 MSS#67
    24. 5.16 ANA#12A
    25.     ANA#32A
    26.     ANA#33A
    27.     ANA#34A
    28.     ANA#35A
    29.     ANA#36
    30.     ANA#37A
    31.     ANA#38A
    32.     ANA#39
    33.     ANA#43
    34.     ANA#44
    35.     ANA#45
    36.     ANA#46
    37.     ANA#47
  7.   Trademarks
  8.   Revision History

5.8 MSS#56

CR4 STC Boot Monitor Failure

Revision(s) Affected:

AWR294`x ES2.0

Description:

Cortex CR4 STC Boot Monitor Failure is observed in the device.

Workaround(s):

It is recommended to execute a sequence (MSS_CTRL:MSS_PBIST_KEY_RST[3:0] = 0) to clear the PBIST registers before starting CR4 (BSS) execution in the Secondary boot loader (SBL). Refer to the SBL example code provided by TI.