SWRZ102C November   2021  – December 2024 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#46
    9. 5.2  MSS#48
    10. 5.3  MSS#49
    11. 5.4  MSS#52
    12. 5.5  MSS#53
    13. 5.6  MSS#54
    14. 5.7  MSS#55
    15. 5.8  MSS#56
    16. 5.9  MSS#57
    17. 5.10 MSS#58
    18. 5.11 MSS#59
    19. 5.12 MSS#60
    20. 5.13 MSS#61
    21. 5.14 MSS#62
    22.     MSS#66
    23. 5.15 MSS#67
    24. 5.16 ANA#12A
    25.     ANA#32A
    26.     ANA#33A
    27.     ANA#34A
    28.     ANA#35A
    29.     ANA#36
    30.     ANA#37A
    31.     ANA#38A
    32.     ANA#39
    33.     ANA#43
    34.     ANA#44
    35.     ANA#45
    36.     ANA#46
    37.     ANA#47
  7.   Trademarks
  8.   Revision History

Revision History

Changes from Revision B (October 2023) to Revision C (December 2024)

  • Advisory to Silicon Variant/Revision Map: Added MSS#66 and MSS#67 advisory in the "Main Subsystem"Go
  • MSS#66: Added a new Advisory "Potential system hang in AXI Initiator Port when MSS Cortex R5 initiates transfer across system boundaries."Go
  • MSS#67: Added a new Advisory "MCRC IP when accessed via multiple Initiators in parallel can cause the IP to hang."Go
  • ANA#45: Updated languageGo

Changes from June 30, 2023 to September 30, 2023 (from Revision A (June 2023) to Revision B (October 2023))

  • (Device Markings) : Updated the section to reflect for AWR2944 ES2.0 silicon markings Go
  • Advisory to Silicon Variant/Revision Map: Added MSS#60, MSS#61, and MSS#62 advisory in the "Main Subsystem"Go
  • MSS#56: Corrected description from Cortex M4 to Cortex CR4Go
  • MSS#60: Added a new Advisory "Mismatch in Read and Write address for 6-internal registers of PCR."Go
  • MSS#61: Added a new Advisory "Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabled."Go
  • MSS#62: Added a new Advisory “HWA hangs when using back to back FFT3X parameter sets."Go
  • ANA#45: Updated language so integrator may implement the workaround.Go
  • ANA#46: Updated language to remove CBUF from the workaround.Go

Changes from March 31, 2023 to June 29, 2023 (from Revision * (March 2023) to Revision A (June 2023))

  • (Device Markings) : Updated the section to reflect for AWR294x ES2.0 silicon markings Go
  • Advisory to Silicon Variant/Revision Map: Added MSS#52, MSS#53, MSS#54, MSS#55, MSS#56, MSS#57, MSS#58 and MSS#59 advisories in the "Main Subsystem"Go
  • Advisory to Silicon Variant/Revision Map: Added ANA#43, ANA#44, ANA#45, ANA#46 and ANA#47 advisories, all silicon revisions in "Analog/milimeter wave"Go
  • Advisory to Silicon Variant/Revision Map: Updated/Revised ANA#32A, ANA#33A, ANA#34A, ANA#35A and ANA#37A in "Analog/milimeter wave"Go
  • MSS#46 : Fixed in AWR294x ES2.0Go
  • MSS#48 : Fixed in AWR294x ES2.0Go
  • CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported: Details and workaround rephrased.Go
  • ANA#32A: Fixed in AWR294x ES2.0 silicon. Inter-TX phase mismatch drift has improved from +/-9 degree in ES1.0 to +/-6 degree in ES2.0. Go
  • ANA#33: Fixed in AWR294x ES2.0 silicon. RX phase mismatch drift has improved from +/-6 degree in ES1.0 to +/-4 degree in ES2.0. Go
  • ANA#34: Low inter-channel TX isolation has been fixed in AWR294x ES2.0. Go
  • ANA#35: Inter-channel RX isolation has improved from 23dB in ES1.0 to 25dB in ES2.0. Go
  • ANA#36 : TX4 phase shifter DAC monitor malfunction has been fixed in AWR294x ES2.0. Go
  • ANA#37: RX gain droop has improved from 6dB in ES1.0 to 4.5dB in ES2.0 across the full operating frequency range. Go
  • ANA#38: Fixed in AWR294x ES2.0. Go