SWRZ115B March   2021  – May 2024 AWR1843AOP

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  6. 5Advisory to Silicon Variant / Revision Map
  7. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#04A
    3.     MSS#05A
    4.     MSS#13
    5.     MSS#17
    6.     MSS#18
    7.     MSS#19
    8.     MSS#20
    9.     MSS#21A
    10.     MSS#22
    11.     MSS#23
    12.     MSS#24
    13.     MSS#25
    14.     MSS#26
    15.     MSS#27
    16.     MSS#28
    17.     MSS#29
    18.     MSS#30
    19.     MSS#31
    20.     MSS#32
    21.     MSS#33
    22.     MSS#34
    23.     MSS#35
    24.     MSS#37B
    25.     MSS#38A
    26.     MSS#39
    27.     MSS#40
    28.     MSS#42
    29.     MSS#43A
    30.     MSS#44
    31.     MSS#45
    32.     ANA#08A
    33.     ANA#09A
    34.     ANA#10
    35.     ANA#11A
    36.     ANA#12A
    37.     ANA#13B
    38.     ANA#15
    39.     ANA#16
    40.     ANA#17A
    41.     ANA#18B
    42.     ANA#20
    43.     ANA#21B
    44.     ANA#22A
    45.     ANA#24A
    46.     ANA#27
    47.     PACKAGE#02A
  8. 7Trademarks
  9. 8Revision History

MSS#32

DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet

Revision(s) Affected:

AWR1843AOP ES1.0

Description:

The BUSY flag in the DMMGLBCTRL register should be set when the DMM starts receiving a packet or has data in its internal buffers. However, the BUSY flag (DMMGLBCTRL.24) may not get set when the DMM starts receiving a packet under the following condition:

  • The BUSY bit is set only after the packet has been received, de-serialized, and written to the internal buffers. It stays active while data is still in the DMM internal buffers. If the internal buffers are empty (meaning that no data needs to be written to the destination memory) then, the BUSY bit will be cleared.

Workaround(s):

Wait for a number of DMMCLK cycles (for example, 95 DMMCLK cycles) beyond the longest reception and deserialization time needed for a given packet size and DMM port configuration, before checking the status of the BUSY flag, and after the DMM ON/OFF bit field (DMMGLBCTRL.[3:0]) has been programmed to OFF.