SWRZ115B March   2021  – May 2024 AWR1843AOP

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  6. 5Advisory to Silicon Variant / Revision Map
  7. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#04A
    3.     MSS#05A
    4.     MSS#13
    5.     MSS#17
    6.     MSS#18
    7.     MSS#19
    8.     MSS#20
    9.     MSS#21A
    10.     MSS#22
    11.     MSS#23
    12.     MSS#24
    13.     MSS#25
    14.     MSS#26
    15.     MSS#27
    16.     MSS#28
    17.     MSS#29
    18.     MSS#30
    19.     MSS#31
    20.     MSS#32
    21.     MSS#33
    22.     MSS#34
    23.     MSS#35
    24.     MSS#37B
    25.     MSS#38A
    26.     MSS#39
    27.     MSS#40
    28.     MSS#42
    29.     MSS#43A
    30.     MSS#44
    31.     MSS#45
    32.     ANA#08A
    33.     ANA#09A
    34.     ANA#10
    35.     ANA#11A
    36.     ANA#12A
    37.     ANA#13B
    38.     ANA#15
    39.     ANA#16
    40.     ANA#17A
    41.     ANA#18B
    42.     ANA#20
    43.     ANA#21B
    44.     ANA#22A
    45.     ANA#24A
    46.     ANA#27
    47.     PACKAGE#02A
  8. 7Trademarks
  9. 8Revision History

Advisory to Silicon Variant / Revision Map

Table 5-1 Advisory to Silicon Variant / Revision Map
Advisory NumberAdvisory TitleAWR1843AOP
Main Subsystem
MSS#03Incorrect Handling of “Saturation” in FFT Hardware Accelerator’s Input / Output Formatter and Statistics BlockX
MSS#04ANumber of Samples (SRCACNT) Should be >3 for Correct Operation of FFT Hardware AcceleratorX
MSS#05AIncorrect FFT Intermediate Stage Clip Status IndicationX
MSS#13Incorrect Read from FFT Hardware Accelerator After Complex Multiplication OperationX
MSS#17Invalid Pre-fetch from MSS CR4 Processor (due to Speculative Read Operation from Tightly Coupled Memory Instance) Leads to Generation of MSS_ESM Group 3 Channel 7: MSS_TCMA_FATAL_ERRX
MSS#18Core Compare Module (CCM-R4F) may Cause nERROR Toggle After First Reset De-assertion Subsequent to Power ApplicationX
MSS#19DMA Read from Unimplemented Address Space may Result in DMA Hang ScenarioX
MSS#20Radar Frame Stuck due to Missing Synchronizer Logic in HardwareX
MSS#21AIssue with HWA Input Formatter 16 bit Real Signed FormatX
MSS#22CAN-FD: Message Transmitted With Wrong Arbitration and Control FieldsX
MSS#23HWA Read Registers Cannot be Read Reliably When the HWA is Executing a ParamSet InstructionX
MSS#24Limitation With Peak Grouping Feature in Hardware AcceleratorX
MSS#25Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset OccursX
MSS#26DMA Requests Lost During Suspend ModeX
MSS#27MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1X
MSS#28A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is EnabledX
MSS#29Spurious RX DMA REQ From a Peripheral Mode MibSPIX
MSS#30MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After ReadingX
MSS#31CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC SpaceX
MSS#32DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A PacketX
MSS#33MibSPI RAM ECC is Not Read Correctly in DIAG ModeX
MSS#34HS Device Does Not Reboot Successfully on Warm Reset Getting Triggered by Watchdog ExpiryX
MSS#35EDMA TPTC Generates an Incorrect Address on the Read Interface, Causing one or More Data Integrity Failures, Hangs, or Extra ReadsX
MSS#37BDCC Module Frequency Comparison can Report Erroneous ResultsX
MSS#38AGPIO Glitch During Power-UpX
MSS#39The state of the MSS DMA is left pending and uncleared on any DMA MPU faultX
MSS#40Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoCX
MSS#42DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application.X
MSS#43A Read-data from internal registers of PCR is not reliable. Shared PCS region protection is also not supported X
MSS#44SYNC IN input pulse wider than 4usec can cause a FRC lockstep errorX
MSS#45Bootup failure during the serial flash busy stateX
Analog / Millimeter Wave
ANA#08ADoppler Spur Observed at Certain RF FrequenciesX
ANA#09ASynthesizer Frequency Nonlinearity around 76.8 GHz when Synthesizer (Chirp) Frequency Monitor EnabledX
ANA#10Unreliable Readings from Synthesizer Supply Voltage MonitorX
ANA#11ATX, RX Gain Calibrations Sensitive to Large External InterferenceX
ANA#12ASecond Harmonic (HD2) Present in the ReceiverX
ANA#13B TX1 to TX3 Phase Mismatch Variation over Temperature is Double that of TX2/TX1 and TX3/TX2 Combinations X
ANA#15Excessive TX-RX Coupling or Reflection can Lead to Saturated RX OutputX
ANA#16LVDS Coupling to Clock SystemX
ANA#17AOn-Board Supply Ringing Induced SpurX
ANA#18BSpurs Caused due to Digital Activity Coupling to XTALX
ANA#20Occasional Failures Observed During Calibration of the Radar SubsystemX
ANA#21BOut of Band Radiated Spectral EmissionX
ANA#22AOvershoot and Undershoot During Inter-Chirp Idle TimeX
ANA#24A40-MHz OSC CLKOUT Causing Spurs in 2D-FFT SpectrumX
ANA#27Digital Temperature Sensor Having Higher ErrorX
Package
PACKAGE#02A Surface Wave Artifact from PCB X