SWRZ115B March   2021  – May 2024 AWR1843AOP

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  6. 5Advisory to Silicon Variant / Revision Map
  7. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#04A
    3.     MSS#05A
    4.     MSS#13
    5.     MSS#17
    6.     MSS#18
    7.     MSS#19
    8.     MSS#20
    9.     MSS#21A
    10.     MSS#22
    11.     MSS#23
    12.     MSS#24
    13.     MSS#25
    14.     MSS#26
    15.     MSS#27
    16.     MSS#28
    17.     MSS#29
    18.     MSS#30
    19.     MSS#31
    20.     MSS#32
    21.     MSS#33
    22.     MSS#34
    23.     MSS#35
    24.     MSS#37B
    25.     MSS#38A
    26.     MSS#39
    27.     MSS#40
    28.     MSS#42
    29.     MSS#43A
    30.     MSS#44
    31.     MSS#45
    32.     ANA#08A
    33.     ANA#09A
    34.     ANA#10
    35.     ANA#11A
    36.     ANA#12A
    37.     ANA#13B
    38.     ANA#15
    39.     ANA#16
    40.     ANA#17A
    41.     ANA#18B
    42.     ANA#20
    43.     ANA#21B
    44.     ANA#22A
    45.     ANA#24A
    46.     ANA#27
    47.     PACKAGE#02A
  8. 7Trademarks
  9. 8Revision History

MSS#39

The state of the MSS DMA is left pending and uncleared on any DMA MPU fault

Revision(s) Affected:

AWR1843AOP ES1.0

Description:

The state of the MSS DMA is left pending and uncleared on any DMA MPU fault. The transfer that caused this MPU fault is left pending inside the DMA IP.

Any trigger on DMA REQ lines (could be caused by any module/IP that is hooked up to DMA in h/w) can re-trigger DMA to start executing the above pending transfer irrespective of whether that trigger is actually valid/enabled in DMA or that module/IP

Workaround(s):

For devices where the Boot ROM is executing the MSS DMA MPU Self tests. As part of application initialization, if the MSS DMA will be used, the following register field should be used to reset the MSS DMA IP so that the uncleared transfer is reset

  1. Write MSS_RCM:SOFTRST1[31:24] 0xAD
  2. Write MSS_RCM:SOFTRST1[31:24] 0x0

It is not recommended to use this configuration at any another instance other than that recommended here in this Errata.

On an actual Real time MPU Error, this error should be treated as a non-recoverable error and a warm reset should be issued to recover.