SWRZ134E April   2023  – October 2024 CC2340R5

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1. 3.1 SPI_04
    2. 3.2 ADC_08
    3. 3.3 ADC_09
    4. 3.4 BATMON_01
    5. 3.5 CLK_01
    6. 3.6 I2C_01
    7. 3.7 GPIO_01
  6. 4Trademarks
  7. 5Revision History

3.2 ADC_08

ADC BUSY bit not cleared in repeat single, sequence, and repeat sequence conversion modes.

Revisions Affected

See Table 1-1

Description

When ADC is configured in repeat single, sequence, or repeat sequence conversion modes with trigger policy as trigger next in the MEMCTLx register, software attempting to stop the conversion sequence by clearing ENC bit does not clear BUSY bit in the STATUS register. In the case of sequence conversion mode with trigger next policy, the BUSY bit is cleared at the end of the conversion sequence.

Workaround

To stop the conversions and to clear the BUSY bit in the above mentioned ADC operating scenario, the following software sequence can be followed.
  1. Write CTL0.ENC = 0
  2. Change CTL1.TRIGSRC to SOFTWARE
  3. Write CTL1.SC=1