SWRZ134E April   2023  – October 2024 CC2340R5

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1. 3.1 SPI_04
    2. 3.2 ADC_08
    3. 3.3 ADC_09
    4. 3.4 BATMON_01
    5. 3.5 CLK_01
    6. 3.6 I2C_01
    7. 3.7 GPIO_01
  6. 4Trademarks
  7. 5Revision History

3.1 SPI_04

Hang scenario with SPI waiting for CPU intervention forever.

Revisions Affected

See Table 1-1

Details

When the CPU is reading or writing the SPI FIFO using FIFO level triggers to generate interrupts, the system can hang. After the first interrupt is serviced, the FIFO level can permanently be below or above the configured threshold and not generate a subsequent CPU interrupt. This can lead to a hang scenario with SPI waiting for CPU intervention forever.

Workaround

  1. Use polling of FIFO status within SPI and do not rely on FIFO level configured interrupts, or
  2. Use only empty/overflow interrupts and do not use FIFO level configured interrupts, or
  3. Use FIFO level configured interrupts along with empty (for TXFIFO) and overflow (for RXFIFO) as a failsafe to avoid hang scenarios.