SWRZ137A December   2022  – March 2024 IWRL6432

PRODUCTION DATA  

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1. 5.1  ANA #48
    2. 5.2  ANA #49
    3. 5.3  ANA #50
    4. 5.4  ANA #51
    5. 5.5  ANA #52
    6. 5.6  DIG #1
    7. 5.7  DIG #2
    8. 5.8  DIG #3
    9. 5.9  DIG #4
    10. 5.10 DIG #5
    11. 5.11 DIG #6
    12. 5.12 DIG #7
    13. 5.13 DIG #8
    14. 5.14 DIG #9
    15. 5.15 DIG #10
    16. 5.16 DIG #14
    17. 5.17 DIG #15
    18. 5.18 DIG #16
  7. 6Trademarks
  8.   Revision History

5.12 DIG #7

APPSS Cortex-M4 doesn't get the correct error response when cluster 3 retention memories are accessed in low-power deep-sleep powered down state

Revision(s) Affected

IWRL6432 ES1.0

Details

The logic to generate error when Cortex-M4F tries to access cluster 3 memories in powered down state is incorrect due to which Cortex-M4F doesn't get the correct error response.

Workaround

Software shouldn't try to access cluster 3 retention memories during low-power deep-sleep powered down state

This has been fixed in ES2.0.