This document describes the known exceptions to the functional and performance specifications to TI CMOS Radar Devices (IWR2944).
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of Radar / millimeter Wave sensor devices. Each of the Radar devices has one of the two prefixes: XIx or IWR2x (for example: IWR2944ABSALT). These prefixes represent evolutionary stages of product development from engineering prototypes (XIx) through fully qualified production devices (IWR2x).
Device development evolutionary flow:
XIx — | Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. |
IWR2x — | Production version of the silicon die that is fully qualified. |
XIx devices are shipped with the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Texas Instruments recommends that these devices not to be used in any production system as their expected end –use failure rate is still undefined.
Figure 3-1 shows an example of the IWR2944 Radar Device's package symbolization.
This identifying number contains the following information:
ADVISORY NUMBER | ADVISORY TITLE | IWR2944 | |
---|---|---|---|
ES1.0 | ES2.0 | ||
MAIN SUBSYSTEM | |||
MSS#25 | Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset Occurs | X | X |
MSS#27 | MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1 | X | X |
MSS#28 | A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is Enabled | X | X |
MSS#29 | Spurious RX DMA REQ From a Peripheral Mode MibSPI | X | X |
MSS#30 | MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading | X | X |
MSS#33 | MibSPI RAM ECC is Not Read Correctly in DIAG Mode | X | X |
MSS#40 | Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC | X | X |
MSS#46 | Hardware Accelerator (HWA) Sniffers as a part of the Measurement Data output (MDO) interface are not operational. | X | |
MSS#48 | Measurement Data Output (MDO) software marker inserted at FIFO threshold location other than for Sniffer 0 is not sent out and is bound to get missed | X | |
MSS#49 | Issues seen in potential interoperability with receiver supporting only Strict Alignment User Flow Control Stripping during Overflow message transmission in Aurora 64B/66B Protocol | X | X |
MSS#52 | DSS L2 Parity Issue: When DSP sends out an access beyond configured memory size | X | X |
MSS#53 | Incorrect behavior seen when context switch happens in the last parameter-set in HWA 2.0 | X | |
MSS#54 | Aurora TX UDP size<=4 is invalid | X | X |
MSS#55 | PMIC CLKOUT dithering in chirp-to-chirp staircase mode not supported | X | X |
MSS#56 | CR4 STC Boot Monitor Failure | X | |
MSS#57 | Loss of data observed on Flush/Marker or completion of packet over MDO interface. | X | X |
MSS#58 | ePWM: Glitch during Chopper mode of operation | X | X |
MSS#59 | CRC: CRC 8-bit data width and CRC8-SAE-J1850 and CRC8-H2F possible use in CAN module is not supported | X | X |
Mismatch in Read and Write address for 6-internal registers of PCR | X |
X |
|
MSS#61 | Data aborts seen while access made to last 24 bytes of the configured MPU region and cache is enabled | X | X |
HWA hangs when using back to back FFT3X paramsets | X |
X |
|
ANALOG / MILLIMETER WAVE | |||
ANA#12A | Second Harmonic (HD2) Present in the Receiver | X | X |
ANA#32A | High inter-TX gain and phase mismatch drift over temperature | X | |
ANA#33A | High inter-RX gain and phase mismatch drift over temperature | X | |
ANA#34A | Low inter-TX isolation between adjacent channels (TX1/TX2 or TX3/TX4) | X | |
ANA#35A | Low inter-RX isolation between adjacent channels (RX1/RX2 or RX3/RX4) | X | X |
ANA#36 | TX4 phase shifter DAC monitor and fault injection not functional | X | |
ANA#37A | High RX gain droop across LO frequency | X | X |
ANA#38 | Return loss on RX pins not meeting the -10dB S11 target | X | |
ANA#39 | HPF cutoff frequency 2800kHz configuration can result in incorrect RX IFA gains and filter corner frequencies | X | X |
ANA#43 | Errors seen in Synthesizer Frequency Live monitor | X | X |
ANA#44 | In 3.3V IO mode, back power is observed on the 1.8V rail from 3.3V rail | X | X |
ANA#45 | Spurs Caused due to Digital Activity | X | X |
ANA#46 | Spurs caused due to data transfer activity | X | X |
ANA#47 | RX Spurs observed across RXs in Idle Channel Scenario | X | X |