Revision(s) Affected:

IWR2944 ES1.0, ES2.0

Description:

The DSP IP is sending out an access to the L2 memory for access beyond the configured DSP L2 memory size of 384 KB (reserved space access) i.e. beyond 0x8085 FFFC.

If parity is enabled, an L2 Parity error is observed for reads to the reserved locations beyond 0x80860000 - 0x8087FFFC

Workaround(s):

Configuring the MPU : ( L2MPPA24- L2MPPA31) to 0.

Write access to reserved space is blocked. No Aliasing & No L2 Parity Error. This ensures the data integrity of valid L2 Region is maintained.

Read access to reserved space still leads to L2 Parity Error (If Parity is enabled).

Debug access(Read & Write) are not blocked: Still leads to Aliasing + L2 Parity Error : Its not feasible to block the debug access despite configuring the MPPA registers for Protection enabled

Memory Protection Fault Address Register(0184 A000h:: L2MPFAR/0184 AC00h:: L1DMPFAR) are populated with the address which are blocked(beyond 384KB boundary in this case) & still accessed

Address(L2MPFAR/L1DMPFAR) & Status(L2MPFSR/L1DMPFSR) Registers are required to be cleared for the next read using Clear registers(L2MPFCR/L1DMPFCR) with values 1

Observations(Both when L1D Cache Enabled/Disabled)

For Read : MPU Protection Errors are observed on L1D with L1MPFAR registers populated with the blocked address access

For Write : MPU Protection Errors are observed on L2 with L2MPFAR registers populated with the blocked address access