MibSPI RX RAM RXEMPTY bit Does Not Get Cleared After Reading
Revision(s) Affected:
IWR2944 ES1.0, ES2.0
Description:
The RXEMPTY flag may not be auto-cleared after a CPU or DMA read when the following conditions are met:
- The TXFULL flag of the latest buffer that the sequencer read out of transmit RAM for the currently active transfer group is 0,
- A higher-priority transfer group interrupts the current transfer group and the sequencer starts to read the first buffer of the new transfer group from the transmit RAM, and
- Simultaneously, the Host (CPU/DMA) is reading out a receive RAM location that contains valid received data from the previous transfers.
Workaround(s):
Avoid transfer groups interrupting one another.
If dummy buffers are used in lower-priority transfer groups, select the appropriate "BUFMODE" for them (like, SKIP/DISABLED) unless, there is a specific need to use the "SUSPEND" mode.