SWRZ162 May   2024 IWR2944

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#25
    2.     MSS#27
    3.     MSS#28
    4.     MSS#29
    5.     MSS#30
    6.     MSS#33
    7.     MSS#40
    8. 5.1  MSS#46
    9. 5.2  MSS#48
    10. 5.3  MSS#49
    11. 5.4  MSS#52
    12. 5.5  MSS#53
    13. 5.6  MSS#54
    14. 5.7  MSS#55
    15. 5.8  MSS#56
    16. 5.9  MSS#57
    17. 5.10 MSS#58
    18. 5.11 MSS#59
    19. 5.12 MSS#60
    20. 5.13 MSS#61
    21. 5.14 MSS#62
    22. 5.15 ANA#12A
    23.     ANA#32A
    24.     ANA#33A
    25.     ANA#34A
    26.     ANA#35A
    27.     ANA#36
    28.     ANA#37A
    29.     ANA#38A
    30.     ANA#39
    31.     ANA#43
    32.     ANA#44
    33.     ANA#45
    34.     ANA#46
    35.     ANA#47
  7.   Trademarks
  8. 6Revision History

MSS#40

Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC

Revision(s) Affected:

IWR2944 ES1.0, ES2.0

Description:

As per TPTC IP Spec, a Transfer request (TR) is supposed to access a single peripheral end point. ACCEL_MEM0/ACCEL_MEM1 memory banks of HWA are available via single peripheral point and ACCEL_MEM2/ ACCEL_MEM3 memory banks of HWA are available as another peripheral point (different from that of ACCEL_MEM0/ ACCEL_MEM1). Hence if a single TR is used to access a buffer spanning ACCEL_MEM1 and ACCEL_MEM2 memories of the HWA (i.e. a single buffer spanning 2 different peripheral points), the spec is not being adhered to. This errata is explicitly highlighting this spec requirement.

Note: The ACCEL_MEM1 and ACCEL_MEM2 memories are referred to as DSS_HWA_DMA0 and DSS_HWA_DMA1 at the SoC level.

Workaround(s):

Split the access into 2 TRs so that a single TR does not span ACCEL_MEM1 +ACCEL_MEM2. The 2 TRs can be chained.