TIDUEM8 Design guide

TIDUEM8B March 2019 – February 2021

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2.3.2.1.7 ADC Setup

Figure 2-8 shows the process used to initialize the ADS131M04. This process is followed when the ADS131M04 is being first setup after the MSP432 MCU resets as well as each time calibration is performed.

Figure 2-8 ADC Initialization and Synchronization Process

Before setting up the ADS131M04 device, the modulator clock of the ADS131M04 is disabled to prevent the ADS131M04 from generating new samples while trying to set it up. The modulator clock is disabled by disabling the SMCLK output of the MSP432 MCU, which is fed to the CLKIN pin of the ADS131M04. Disabling the SMCLK output only needs to be done after calibration and not after an MSP432 MCU reset event since the SMCLK clock output is automatically not output after the MSP432 MCU resets.

After the SMCLK output is disabled, the EUSCIB0 SPI module of the MSP432 MCU is configured for communication to the ADS131M04 device. The EUSCIB0 SPI module is specifically configured as a master device that uses 3-wire mode (the chip select signal is manually asserted high and low in the test software instead of using the chip select feature of the SPI module) and has an 8.192-MHz SPI clock that is derived from the 8.192-MHz SMCLK clock. After the SPI is setup, all interrupts are disabled and a reset command is sent from the MSP432 MCU to the ADS131M04 via SPI. Interrupts are then re-enabled and the MSP432 MCU sends commands to the ADS131M04 to configure its registers.

At this point, note that the modulation clock is not output by the MSP432 MCU yet, which means that sampling is not started yet. By sending commands to the ADS131M04 to initialize the ADS131M04 registers, the ADS131M04 is configured for the following:

MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the ADS131M04 packet, DRDY signal asserted on most lagging enabled channel, DRDY asserted high when conversion value is not available, DRDY asserted low when conversion values are ready
GAIN1 register settings: PGA gain of 1 used for all four ADC channels
CFG register settings: Current detection mode disabled
CHx_CNG register settings (where x is the channel number)
- Two-voltage mode: All four ADC channel inputs connected to external ADC pins and channel phase delay set to 0 for each channel (note that software phase compensation is used instead of ADS131M04 hardware phase compensation)
- One-voltage mode: Channels 0, 1, and 2 inputs connected to external ADC pins and channel phase delay set to 0 for channels 0, 1, and 2 (note that software phase compensation is used instead of ADS131M04 hardware phase compensation); the channel 3 config register is not modified since channel 3 is not used for this configuration.
CLOCK register settings: 512 OSR, all channels enabled, and high-resolution modulator power mode

After the ADS131M04 registers are properly initialized, the MSP432 MCU is configured to generate a port interrupt whenever a falling edge occurs on the DRDY pin, which would indicate that the ADS131M04 has new current samples that are available. Next, the MSP432 MCU outputs the SMCLK clock to the ADS131M04, which starts the voltage and current sampling.

The ADS131M04 modulator clock is derived from the clock fed to its CLKIN pin, which is output from the SMCLK output of the MSP432 MCU. The clock fed to the CLKIN pin of the ADS131M04 device is internally divided by two, to generate the ADS131M04 modulator clock. The sampling frequency of the ADS131M04 is therefore defined as f_s = f_M / OSR = f_CLKIN / (2 × OSR), where f_s is the sampling rate, f_M is the modulator clock frequency, f_CLKIN is the clock fed to the ADS131M04 CLKIN pin, and OSR is the selected oversampling ratio. In this design, the SMCLK clock of the MSP432 MCU that is fed to the ADS131M04 CLKIN pin has a frequency of 8.192 MHz. The oversampling ratio is selected to be 512 . As a result, the ADS131M04 modulator clock is set to 4.096 MHz and the sample rate is set to 8000 samples per second.

For a two-voltage system where each line-to-neutral voltage is measured, at least four ADC channels are necessary to independently measure two voltages and two currents. In this design, the following ADS131M04 channel mappings are used in software for the two-voltage configuration:

AIN0P and AIN0N ADS131M04 ADC channel pins → Current I1 (Phase A Current)
AIN1P and AIN1N ADS131M04 ADC channel pins → Current I2 (Phase B Current)
AIN2P and AIN2N ADS131M04 ADC channel pins → Voltage V1 (Phase A Line-to-Neutral Voltage)
AIN3P and AIN3N ADS131M04 ADC channel pins → Voltage V2 (Phase B Line-to-Neutral Voltage)

For a balanced split-phase system, each line-to-neutral voltage should be half of the line-to-line voltage. In the one-voltage configuration of this design, only the line-to-line voltage is measured. The line-to-line voltage readings are divided by two (this division is done automatically by following the calibration process) to get the line-to-neutral voltages of each phase. As a result, the same ADC samples are used in the software to calculate the RMS voltage and power for the two phases. This configuration uses three ADC channels: one to measure the line-to-line voltage and the other two for the two currents. In this design, the following ADS131M04 channel mappings are used in software for the one-voltage configuration:

AIN0P and AIN0N ADS131M04 ADC channel pins → Current I1 (Phase A Current)
AIN1N and AIN1P ADS131M04 ADC channel pins → Current I2 (Phase B Current)
AIN2P and AIN2N ADS131M04 ADC channel pins → Line-to-Line Voltage (Phase A line voltage - Phase B line voltage)
AIN3P and AIN3N ADS131M04 ADC channel pins → Not used in design

Since the line-to-line voltage measured in the one-voltage configuration is the Phase A line voltage - Phase B line voltage and not the Phase B line voltage - Phase A line voltage, the orientation for phase B current should be reversed, which is done by either swapping where the positive and negative output terminals of the current transformers of Phase B are connected, swapping the polarity of the current fed to the Phase B current input in the design, or by using the same input current and CT output terminal polarity at phase A and just negating the current channel ADC channels in software. To prevent having to do any hardware changes when switching from two-voltage to one-voltage modes, this design reverses the polarity of the current channels by choosing the option where the phase B current channel values are negated in the test software.