TIDUEM8B March   2019  – February 2021

 

  1.   1
  2.   2
  3.   3
  4.   4
  5.   5
  6.   6
    1.     7
      1.      8
      2.      9
    2.     10
  7.   11
    1.     12
    2.     13
      1.      14
      2.      15
      3.      16
      4.      17
      5.      18
      6.      19
      7.      20
      8.      21
      9.      22
      10.      23
    3.     24
      1.      25
        1.       26
        2.       27
        3.       28
        4.       29
          1.        30
          2.        31
      2.      32
        1.       33
          1.        34
          2.        35
          3.        36
          4.        37
          5.        38
          6.        39
          7.        40
        2.       41
          1.        42
        3.       43
          1.        44
            1.         45
            2.         46
          2.        47
          3.        48
  8.   49
    1.     50
      1.      51
      2.      52
        1.       53
          1.        54
          2.        55
        2.       56
      3.      57
    2.     58
      1.      59
        1.       60
        2.       61
        3.       62
          1.        63
          2.        64
            1.         65
            2.         66
              1.          67
                1.           68
                2.           69
              2.          70
              3.          71
      2.      72
        1.       73
        2.       74
  9.   75
    1.     76
    2.     77
    3.     78
      1.      79
    4.     80
    5.     81
    6.     82
  10.   83
    1.     84
  11.   85
  12.   86
2.3.1.4.2 Current Measurement Analog Front End

The analog front end for current inputs is different from the analog front end for the voltage inputs. Figure 2-6 shows the analog front end used for a current channel, where the positive and negative leads from a CT are connected to pins 1 and 3 of header J26.

GUID-A3352171-3F60-480F-A0C0-4521D65602C3-low.gifFigure 2-6 Analog Front End for Current Inputs

The analog front end for current consists of footprints for electromagnetic interference filter beads (R89 and R90), burden resistors for current transformers (R91 and R92), and an RC low-pass filter (R94, R95, C97, C98, and C99) that functions as an anti-alias filter. There are also footprints (U21 and U22) that can be replaced with the TVS0500 for supplemental protection from surges, if required.

As Figure 2-6 shows, resistors R91 and R92 are the burden resistors, which are in series with each other. For best THD performance, instead of using one burden resistor, two identical burden resistors in series are used with the common point being connected to GND. This split-burden resistor configuration ensures that the waveforms fed to the positive and negative terminals of the ADC are 180 degrees out of phase with each other, which would provide the best THD results with this ADC. The total burden resistance is selected based on the current range used and the turns ratio specification of the CT (this design uses CTs with a turns ratio of 2000). The total value of the burden resistor for this design is 12.98 Ω.

Equation 2 shows how to calculate the range of differential voltages fed to the current ADC channel for a given maximum current, CT turns ratio, and burden resistor value.

Equation 2. GUID-70268A12-B6B8-4654-ACE7-4DD61EC4C132-low.gif

Based on the maximum current of 100 A, CT turns ratio of 2000, and burden resistor of 12.98 Ω, of this design, the input signal to the current ADC has a voltage swing of ±918 mV maximum (649 mVRMS) when the maximum current rating of the meter (100 A) is applied. This ±918-mV maximum input voltage is well within the ±1.2-V input range of the device for the selected PGA gain of 1 that is used for the current channels.

Note that the pin order of the AINxP and AINxN pins on the ADS131M04 is swapped when going from one converter to another. As an example, AIN0P is pin 3 and AIN0N is pin 4 but AIN1N is pin 5 and AIN1P is pin 6. The swapped order is why the order of the CT positive output terminal and negative output terminal is swapped between the J26 current input terminal block of Phase A and the J27 current input terminal block of Phase B.