TIDUF06 August   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PCB and Form Factor
      2. 2.2.2 Power Supply Design
        1. 2.2.2.1 POC Filter
        2. 2.2.2.2 Power Supply Considerations
          1. 2.2.2.2.1 Choosing External Components
          2. 2.2.2.2.2 Choosing the Buck 1 Inductor
          3. 2.2.2.2.3 Choosing the Buck 2 and Buck 3 Inductors
          4. 2.2.2.2.4 Functional Safety
    3. 2.3 Highlighted Products
      1. 2.3.1 DS90UB953-Q1
      2. 2.3.2 TPS650330-Q1
      3. 2.3.3 IMX623
    4. 2.4 System Design Theory
  8. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Required Hardware
      1. 3.1.1 Hardware Setup
      2. 3.1.2 FPD-Link III I2C Initialization
      3. 3.1.3 IMX623 Initialization
    2. 3.2 Testing and Results
      1. 3.2.1 Test Setup
        1. 3.2.1.1 Power Supplies Startup
        2. 3.2.1.2 Power Supply Startup – 1.8 V Rail and Serializer PDB Setup
      2. 3.2.2 Test Results
        1. 3.2.2.1 Power Supplies Start Up
        2. 3.2.2.2 Power Supply Output Voltage Ripple
        3. 3.2.2.3 Power Supply Load Currents
        4. 3.2.2.4 I2C Communications
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 PMIC Layout Recommendations
      2. 4.3.2 PCB Layer Stackup
      3. 4.3.3 Serializer Layout Recommendations
      4. 4.3.4 Imager Layout Recommendations
      5. 4.3.5 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Related Documentation
  11. 6Trademarks

4.3.4 Imager Layout Recommendations

CSI-2 lane routing must follow the same guidelines previously outlined for the imager layout. Similarly, decoupling capacitors should be placed as close as possible to the supply pins, with smaller capacitors taking priority in terms of distance to the pin. Minimize the parasitic resistance and inductance to the ground plane with vias and wide traces.