TIDUF84 June   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 UCC28810
      2. 2.3.2 MCF8315
      3. 2.3.3 MSPM0L
      4. 2.3.4 MSPM0C
  9. 3System Design Theory
    1. 3.1 MCF8315 Design
      1. 3.1.1 Power section
      2. 3.1.2 GPIO section
    2. 3.2 ACDC Design: Single Stage PFC
    3. 3.3 Host MCU Design
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Hardware Overview
      2. 4.1.2 TIDA-010951 PCB
    2. 4.2 Software Requirements
    3. 4.3 Testing requirements
    4. 4.4 Test Setup
    5. 4.5 Test Results
      1. 4.5.1 Power Management in TIDA-010951
      2. 4.5.2 UCC28810 Based Single Stage PFC
      3. 4.5.3 BLDC Residential Fan Operation Using MCF8315C
        1. 4.5.3.1 Power-Up Sequence
        2. 4.5.3.2 Forward Windmilling (ISD Forward Resync)
        3. 4.5.3.3 Reverse Windmilling (ISD Reverse Resync)
        4. 4.5.3.4 Direction Reversal
        5. 4.5.3.5 Fan Acceleration/Deceleration
      4. 4.5.4 Thermal Performance
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Recognition

ACDC Design: Single Stage PFC

This single-stage power factor corrected converter is an isolated flyback AC/DC topology that rectifies the AC input line to a DC output with an input sinusoidal current. The single-stage flyback topology is widely used as an isolated LED driver design and some applications need PFC and flyback AC/DC, to achieve high power factor with low component count, high reliability, and low cost without a large size 450VDC bulk capacitor.

The basic principle of the circuit are as follows:

From the input side, a 3.15A fuse is placed to protect overcurrent, an MOV is placed to protect overvoltage, and an NTC is placed to suppress the start-up inrush current. L1, L2, C3, C1 are input EMI filters, and D1 is a bridge rectifier. D2, D3, R1, R2, R3 form an input voltage detection circuit, R4, R5, C10, D13 form a high-voltage start-up circuit, and enter VSENSE through R13, R14 voltage division. Q1 is the primary power switch, and R16, D14, R17 help control the switching speed. R23 connected in series on the source is the primary current sensing resistor, and the T1 bias winding also provides a transformer zero energy (TZE) detection signal (transmitted to the TZE pin of U1 via R21, R20, C12). R11, D10, and D9 connected in parallel on the primary winding of the transformer form a clamping circuit on the drain of Q2.

D6, C5, C6, and C7 form a secondary rectifier filter circuit. The TL431 circuit formed by U3 feeds back the signal to EAOUT through an optocoupler. In this design, we set the feedback voltage to 24.18V .U1 detects the AC input voltage through the pin VINS, which can force the peak switch current to track the change of the input voltage, thereby improving the system power factor. C16,R18,D11,R20,Q3,R22,Q2 as a leading edge blanking circuit, for the detail information you can check the description of “Leading Edge Blanking Circuit on the TZE Pin” in the UCC28810 data sheet.

TIDA-010951 Single Stage PFC
                    Design Figure 3-3 Single Stage PFC Design