The ADS4249 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance and consume extremely low power with a 1.8-V supply. This topology makes the ADS4249 well-suited for multi-carrier, wide-bandwidth communications applications.
The ADS4249 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™ package.
The device includes internal references and the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4249 is specified over the industrial temperature range (–40°C to 85°C).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS4249 | VQFN (64) | 9.00 mm × 9.00 mm |
Changes from D Revision (May 2015) to E Revision
Changes from C Revision (July 2012) to D Revision
Changes from B Revision (September 2011) to C Revision
Changes from A Revision (September 2011) to B Revision
65 MSPS | 125 MSPS | 160 MSPS | 250 MSPS | |
---|---|---|---|---|
ADS422x 12-bit family |
ADS4222 | ADS4225 | ADS4226 | ADS4229 |
ADS424x 14-bit family |
ADS4242 | ADS4245 | ADS4246 | ADS4249 |
The ADS4249 is pin-compatible with the previous generation ADS62P49 data converter; this similar architecture enables easy migration. However, there are some important differences between the two device generations, summarized in Table 1.
ADS62P49 | ADS4249 |
---|---|
PINS | |
Pin 22 is NC (not connected) | Pin 22 is AVDD |
Pins 38 and 58 are DRVDD | Pins 38 and 58 are NC (do not connect, must be floated) |
Pins 39 and 59 are DRGND | Pins 39 and 59 are NC (do not connect, must be floated) |
SUPPLY | |
AVDD is 3.3 V | AVDD is 1.8 V |
DRVDD is 1.8 V | No change |
INPUT COMMON-MODE VOLTAGE | |
VCM is 1.5 V | VCM is 0.95 V |
SERIAL INTERFACE | |
Protocol: 8-bit register address and 8-bit register data | No change in protocol New serial register map |
EXTERNAL REFERENCE | |
Supported | Not supported |
NOTE:
The PowerPAD is connected to DRGND.PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 17 | I | Analog ground |
18 | |||
21 | |||
24 | |||
27 | |||
28 | |||
31 | |||
32 | |||
AVDD | 16 | I | Analog power supply |
22 | |||
33 | |||
34 | |||
CLKM | 26 | I | Differential clock negative input |
CLKP | 25 | I | Differential clock positive input |
CLKOUTP | 57 | O | Differential output clock, true |
CLKOUTM | 56 | O | Differential output clock, complement |
CTRL1 | 35 | I | Digital control input pins. Together, these pins control the various power-down modes. |
CTRL2 | 36 | ||
CTRL3 | 37 | ||
DA0M | 40 | O | Channel A differential output data pair, D0 and D1 multiplexed |
DA0P | 41 | ||
DA2M | 42 | O | Channel A differential output data D2 and D3 multiplexed |
DA2P | 43 | ||
DA4M | 44 | O | Channel A differential output data D4 and D5 multiplexed |
DA4P | 45 | ||
DA6M | 46 | O | Channel A differential output data D6 and D7 multiplexed |
DA6P | 47 | ||
DA8M | 50 | O | Channel A differential output data D8 and D9 multiplexed |
DA8P | 51 | ||
DA10M | 52 | O | Channel A differential output data D10 and D11 multiplexed |
DA10P | 53 | ||
DA12M | 54 | O | Channel A differential output data D12 and D13 multiplexed |
DA12P | 55 | ||
DB0M | 60 | O | Channel B differential output data pair, D0 and D1 multiplexed |
DB0P | 61 | ||
DB2M | 62 | O | Channel B differential output data D2 and D3 multiplexed |
DB2P | 63 | ||
DB4M | 2 | O | Channel B differential output data D4 and D5 multiplexed |
DB4P | 3 | ||
DB6M | 4 | O | Channel B differential output data D6 and D7 multiplexed |
DB6P | 5 | ||
DB8M | 6 | O | Channel B differential output data D8 and D9 multiplexed |
DB8P | 7 | ||
DB10M | 8 | O | Channel B differential output data D10 and D11 multiplexed |
DB10P | 9 | ||
DB12M | 10 | O | Channel B differential output data D12 and D13 multiplexed |
DB12P | 11 | ||
DRGND | 49 | I | Output buffer ground |
PAD | |||
DRVDD | 1 | I | Output buffer supply |
48 | |||
INM_A | 30 | I | Differential analog negative input, channel A |
INP_A | 29 | I | Differential analog positive input, channel A |
INM_B | 20 | I | Differential analog negative input, channel B |
INP_B | 19 | I | Differential analog positive input, channel B |
NC | 38 | — | Do not connect, must be floated |
39 | |||
58 | |||
59 | |||
RESET | 12 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 13 | I | This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode selection when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor. |
SDATA | 14 | I | Serial interface data input; this pin has an internal 150-kΩ pull-down resistor. |
SDOUT | 64 | O | This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state. |
SEN | 15 | I | This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD. |
VCM | 23 | O | This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins |
NOTE:
The PowerPAD is connected to DRGND.PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 17 | I | Analog ground |
18 | |||
21 | |||
24 | |||
27 | |||
28 | |||
31 | |||
32 | |||
AVDD | 16 | I | Analog power supply |
22 | |||
33 | |||
34 | |||
CLKM | 26 | I | Differential clock negative input |
CLKP | 25 | I | Differential clock positive input |
CLKOUT | 57 | O | CMOS output clock |
CTRL1 | 35 | I | Digital control input pins. Together, these pins control various power-down modes. |
CTRL2 | 36 | ||
CTRL3 | 37 | ||
DA0 | 40 | O | Channel A ADC output data bits, CMOS levels |
DA1 | 41 | ||
DA2 | 42 | ||
DA3 | 43 | ||
DA4 | 44 | ||
DA5 | 45 | ||
DA6 | 46 | ||
DA7 | 47 | ||
DA8 | 50 | ||
DA9 | 51 | ||
DA10 | 52 | ||
DA11 | 53 | ||
DA12 | 54 | ||
DA13 | 55 | ||
DB0 | 60 | O | Channel B ADC output data bits, CMOS levels |
DB1 | 61 | ||
DB2 | 62 | ||
DB3 | 63 | ||
DB4 | 2 | ||
DB5 | 3 | ||
DB6 | 4 | ||
DB7 | 5 | ||
DB8 | 6 | ||
DB9 | 7 | ||
DB10 | 8 | ||
DB11 | 9 | ||
DB12 | 10 | ||
DB13 | 11 | ||
DRGND | 49 | I | Output buffer ground |
PAD | |||
DRVDD | 1 | I | Output buffer supply |
48 | |||
INM_A | 30 | I | Differential analog negative input, channel A |
INP_A | 29 | I | Differential analog positive input, channel A |
INM_B | 20 | I | Differential analog negative input, channel B |
INP_B | 19 | I | Differential analog positive input, channel B |
NC | 38 | — | Do not connect, must be floated |
39 | |||
58 | |||
59 | |||
RESET | 12 | I | Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor. |
SCLK | 13 | I | This pin functions as a serial interface clock input when RESET is low. SCLK controls the low-speed mode when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor. |
SDATA | 14 | I | Serial interface data input; this pin has an internal 150-kΩ pull-down resistor. |
SDOUT | 64 | O | This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state. |
SEN | 15 | I | This pin functions as a serial interface enable input when RESET is low. SEN controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD. |
UNUSED | 56 | — | This pin is not used in the CMOS interface |
VCM | 23 | O | This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins |