Introduction

Supporting high-voltage common-mode input in the range of ±30 V is a common requirement for programmable logic controller (PLC) analog input modules. One way to support high-common mode is with signal passive scaling in front of instrumentational amplifier similar to the circuit shown in Figure 1.

An instrumentation amplifier similar to INA826 can be used along with matched resistors. The gain of this circuit is represented as:

When examining the performance of this circuit with G₁=0.249, and G₂=4.01, for example, overall unity gain is achieved for the interface. These gains can be achieved with 0.1% standard resistors R_f=249 kΩ, R_i=750 kΩ, R_G=16.4 kΩ.

Common-Mode Range

With the aforementioned values, input voltages of the amplifier are

Where V_i and V_CM are the differential input and common-mode input voltages, respectively.

If V_i range of ±10 V is assumed, we can determine the V_CM range given the input voltages derived above. The instrumentational amplifier valid input range is complex to calculate, and depends on power supply levels and gain.

We can use Figure 2 function in TI's Analog engineer's calculator tool as shown in Figure 2 to quickly calculate the common-mode range assuming bipolar supply of ±15 V and Vref=0. Using the tool shows Vcm at the amplifier input limits are 9.05 V and -10.7 V, by calculating back the input terminal common-mode range we come to the following values: -42.9 V to +36.3 V

Input Impedance

Input impedance of the circuit in Figure 1 is:

With chosen resistor values, 1 MΩ, and 2 MΩ, respectively.

Offset Error

While input impedance is determined only by font-end, both front-end and the ADC are affecting other parameters like offset and gain errors. Figure 3 shows the front-end connected to the simultaneous sampling ADS8588S.

Using the sum of squares, we can calculate the overall offset of the signal chain at the input of the ADC as:

Where ADC offset is input-referred, and amplifier offset is output-referred. Both ADC and amplifier offsets and offset drifts are found in respective data sheets. Figure 4 shows the offset and offset drift distribution for INA826.

Initial offset can be eliminated using calibration, while offset drift contributes to uncompensated offset error over temperature. At low gains, output offset dominates the instrumentational amplifier offset. INA826 offset typical value is 200 µV, and drift value is about 2 µV/℃, this leads to ±0.12 mV over -40 ℃ to 85 ℃.

ADC8588S features a typical offset of 150 µV and a negligible offset drift of 0.3 ppm/℃. The applying offset equation above we get a typical RMS total offset of 250 µV and 2 µV/℃. It’s worth noting that worst-case offset values are way above this. However, the worst-case values are too pessimistic and typical values are much more realistic.

CM-related Offset Error

When CM voltage is added to a zero-input voltage, another component of offset is introduced due to the input resistors mismatch which is dependent on the common-mode gain.

Where ΔR/R is the resistor tolerance, and α is equals 4 in case of worst-case calculation, and 0.33 for the typical case. CM-induced offset error can be calculated by multiplying this gain by the common-mode range.

Using 0.1% resistors, and a CMR=±35 V, V_OS|_CM=±2.9 mV. This shows that whenever CM is present, it dominates the offset error. This type of offset error cannot be eliminated by calibration.

Gain Error

For the full chain, gain error consists of three components: resistors, amplifier, and ADC

The resistors gain error ε_G1 can be estimated using Monte-Carlo simulation based on the given resistor tolerance (0.1%). The simulation results show a three-sigma value of (0.125%). The amplifier typical intrinsic gain error is 0.03% according to data sheet, so the amplifier gain error will be dominated by gain setting resistor R_g tolerance (0.1%). The ADC typical gain error is ±4 LSB=0.01% which is negligible. Substituting these values, we get 0.16% as overall gain error. This translates to 16 mV gain error in case of 10 V input range.

In case of non-zero common mode, the CM-related offset error would appear as gain error, by adding both values, the full-scale error would be close to 19 mV or 0.19%.

Signal Bandwidth

The signal goes over three subsequent filters through the signal chain.

1. The RC filter of the front-end.
2. The bandwidth of the INA826.
3. The bandwidth of the ADS8588S.

Combining these filters leads to an overall bandwidth of 21 kHz. This bandwidth will result in a 0.01% linear settling time of 70 µs.

1. RC filter of 750 kΩ and 1pF differential input impedance has 212 kHz of bandwidth
2. INA826 bandwidth is about 700 kHz
3. ADS8588 has an integrated filter with 24-kHz bandwidth

Full-scale Error

At full-scale input, in addition to non-zero common-mode several errors are added to get the full-scale error.

Common-Mode Rejection Ratio

It can be proven that CMRR due to resistor mismatch (R_f and R_ƒ, Ri_i and R_i’) equals:

Typical value calculation leads to CMRR_R = 3784 (71.5dB).

Test Results

The analog signal chain shown in Figure 3 is put under test to validate calculations presented in this article. Note that some statistical parameters like offset error cannot be really validated using a single device sample.

Table 1 shows the measured parameters of few input channels attached to one ADC. Measured results to a great extent matches our previous calculation. The settling time is higher than calculated probably due to non-linear settling effect. Gain error is also lower than calculated, which might be attributed to limited sampling. The techniques introduced in this document can also be applied to the instrumentation amplifiers listed in Table 2.

References

1. Texas Instruments, Difference Amplifier (subcontractor) Circuit, Analog Engineer's Circuit: Amplifiers.
2. Texas Instruments, 16-bit 8-Channel PLC Analog Input Module with High Voltage CM support, application brief.