SLAAEB9 February 2024 MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
This subsystem demonstrates how the internal ADC, and math accelerator (MATHACL) modules within the MSPM0G family of devices can be used to implement a simple, streaming IIR filter of an analog signal. In this configuration, noise on an analog signal is filtered using a single pole IIR filter. The defined beta value can be adjusted to control the IIR filter decay over frequency.
This application requires an integrated ADC, MathACL, and DAC12 modules.
Sub-block Functionality | Peripheral Use | Notes |
---|---|---|
Analog Signal Capture | (1×) ADC | Shown as ADC12_0_INST in code |
IIR Filter | (1×) MathACL | Shown as MATHACL in code |
Analog Signal Output (Optional) | (1×) DAC12 | Shown as DAC12_0_INST in code |